Xilinx LogiCORE IP, User Manual

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Video Scaler v4.0 User Guide www.xilinx.com 43
UG805 March 1, 2011
Coefficient Interface
An address-multiplexer is used to support the coefficient write interface as shown in
Figure 8-2 . The coefficient write-address is multiplexed with the coefficient read-address
for the vertical filter to create the address for Port A on the dual-port coefficient RAM.
Consequently, coefficients must be loaded into the coefficient stores when no active video
scaling is occurring. It is only possible, therefore, to load the coefficients during the vertical
blanking period. Since this would be an impossible burden on a processor, an external
block RAM FIFO has been provided to which you load your coefficients during one frame
period, as shown in
Figure 8-2 . Following a latency period after the positive transition of
vblank_in
, any new coefficient set is streamed into the internal coefficient store for use
by the filter in the next frame.
A waveform indicating the coefficient loading process is shown in Figure 8-3 .
The coefficient memory interface is an asynchronous interface. A high level on the
coef_wr_en
signal is used to capture the coefficients delivered on
coef_data_in
as
shown in Figure 8-3 . An internal state-machine detects the 3rd ‘clk’ period when
coef_wr_en
is stable and high. At this point, the data is registered into the FIFO. Xilinx
recommends that the high
coef_wr_en
pulse be no less than the equivalent of 6 ‘clk’
periods in duration. It is required that it also be low for a period no less than 6 ‘clk’ periods
between write operations.
The guidelines are as follows:
• The address
coef_set_addr
for all coefficients in one set must be written via the
normal register interface.
•
coef_data_in
delivers two coefficients per 32-bit word. The lower word (bits 15:0)
always holds the coefficient that will be applied to the latest tap (that is, spatially
speaking, the right-most or lowest). The word format is shown in
Figure 8-1 .
• All coefficients for one phase must be loaded sequentially via
coef_data_in
,
starting with coef 0 and coef 1 [coef 0 is applied to the newest (right-most or lowest)
input sample in the current filter aperture]. See Figure 8-3 . For an odd number of
coefficients, the final upper 16 bits is ignored.
• All phases must be loaded sequentially starting at phase 0, and ending at phase
(
max_phases-1
). This must always be observed, even if a particular set of
coefficients has fewer active phases than
max_phases
.
• For RGB/4:4:4 , when not sharing coefficients across H and V operations, for each
dimension, one bank of coefficients must be loaded into the FIFO before they can be
streamed into the coefficient memory. When sharing coefficients across H and V
operations, it is only necessary to write coefficients for the H operation. This process is
permitted to take as much time as desired by the user system. This means that worst
X-Ref Target - Figure 8-2
Figure 8-2: Coefficient Loading Mechanism, Including External FIFO
v b l a nk_in
Coefficient Lo a d
Control S M
Coefficient Lo a d
FIFO
Coefficient S tore coef_d a t a _in( 3 1:0)
coef_ s et_wr_ a ddr( 3 :0)
coef_wr_en
Coefficient Write
Addre
ss
Coefficient s
to filter s
Video S c a ler
Port A
Oper a tion a l Re a d
Addre ss (V Filter)
Oper a tion a l Re a d
Addre ss (H Filter)
Port B
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