Xilinx LogiCORE IP, User Manual

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Video Scaler v4.0 User Guide www.xilinx.com 77
UG805 March 1, 2011
Register Definitions
Table B-2: control Register
0x0000 control R/W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reserved enable
Name Bits Description
Reserved 31:3 Reserved
Timing_Gen_Enable 2
Timing Generator enabled into video scaler. This bit
enables the timing generator signals, vblank, hblank,
active video to go through to the signals on the video
scaler core.
Reg_Update_Enable 1
Register Update enable. This bit communicates to the IP
core to take new values at the next frame vblank rising
edge. The registers that utilize this bit are 0x0010 through
0x0038.
Usage: This bit is cleared when the IP core next vblank
happens.
Enable 0 Enable the Video Scaler core on the next video frame.
Table B-3: reserved Register
0x0004 status R/W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reserved C
Name Bits Description
Reserved 31:1 Reserved
Coef_write_rdy 0
If this bit is '1' then the Coeffs can be written into the core.
Check at the beginning of a coeff transfer.
Table B-4: status Register
0x0008 status_error R
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Error_Code3 Error_Code2 Error_Code1 Error_Code0
Name Bits Description
Error_Code3 31:24 Error codes to be defined