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Xilinx LogiCORE IP, User Manual

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Xilinx LogiCORE IP User Manual Download Page 74

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www.xilinx.com

Video Scaler v4.0 User Guide

UG805 March 1, 2011

Appendix A:

Use Cases

Summary of Contents for LogiCORE IP

Page 1: ...LogiCORE IP Video Scaler v4 0 User Guide UG805 March 1 2011...

Page 2: ...istributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior w...

Page 3: ...erience 15 Additional Core Resources 15 Documentation 15 Technical Support 15 Providing Feedback 16 Core 16 Documentation 16 Nomenclature 16 Chapter 2 Overview Chapter 3 Implementation Basic Architect...

Page 4: ...Driver 37 Coefficient Delivery for EDK pCore Interface 37 Interrupts 37 Chapter 7 Scaler Aperture Input Aperture Definition 39 Cropping 40 Chapter 8 Coefficients Coefficient Table 41 Coefficient Inter...

Page 5: ...ction Calls 88 L1 API Function Calls 89 L2 API Function Calls 89 Example Settings 90 Pass Thru 90 Down Sample by 2 in Horizontal and Vertical 91 Appendix C System Level Design Introduction 93 Example...

Page 6: ...Video Scaler v4 0 User Guide www xilinx com UG805 March 1 2011...

Page 7: ...ation 8 bits 28 Chapter 5 Scaler Architectures Figure 5 1 Internal Data Path Bitwidths for Single Engine YC Mode 29 Figure 5 2 Internal Data Path Bitwidths for Dual Engine YC Mode 30 Figure 5 3 Intern...

Page 8: ...1280 220 x VSF 480 720 72 Figure A 3 Zoom Up scaling HSF 220 x 480 1280 VSF 220 x 270 720 72 Figure A 4 Shrink Down scaling Example for Picture in Picture PinP HSF 220 x 1280 480 VSF 220 x 720 270 72...

Page 9: ...e 8 3 Example 1 Coefficient Set Download Format 45 Table 8 4 Example 2 Coefficient Set Download Format 47 Table 8 5 Example 9 Tap Coefficients 49 Table 8 7 Example 3 Coefficient Set Download Format 50...

Page 10: ...0 Table B 13 start_hpa_y Register 80 Table B 14 start_vpa_y Register 81 Table B 15 start_hpa_c Register 81 Table B 16 start_vpa_c Register 81 Table B 17 Coefficient_write_set_address Register 81 Table...

Page 11: ...ut signals and their relation to the output data Chapter 5 Scaler Architectures describes Single engine for sequential YC processing Dual Engine for parallel YC processing and Triple engine for parall...

Page 12: ...rade 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild design_name Helvetica bold Commands that you select from a menu File Open Keyboard shortcuts Ctrl C Italic fon...

Page 13: ...me loc1 loc2 locn Notations The prefix 0x or the suffix h indicate hexadecimal notation A read of address 0x00112975 returned 45524943h An _n means the signal is active low usr_teof_n is active low Co...

Page 14: ...14 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Preface About This Guide...

Page 15: ...n and functionality of the application For best results previous experience building high performance pipelined FPGA designs using Xilinx implementation software and UCF is recommended Contact your lo...

Page 16: ...er Aperture The input data rectangle used to create the output data rectangle Filter Aperture The group of contributory data used in a filter to generate one particular output The number of elements i...

Page 17: ...conversion of one frame It includes all phases For an n tap m phase filter a coefficient bank comprises nxm values Each tap may be multiplied by any one of m coefficients assigned to it selected by th...

Page 18: ...18 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 1 Introduction...

Page 19: ...uire shrink and zoom functionality The Xilinx Video Scaler supports real time video inputs and memory interface inputs that is a frame buffer When connected to a real time input source the input clock...

Page 20: ...20 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 2 Overview...

Page 21: ...re controller Whatever the configuration you must assess given the clock frequency available how much time is available for scaling and define 1 Whether to source the scaler using live video or an inp...

Page 22: ...d the scope of the control state machines To support the many possibilities of input and output configurations and to take advantage of the fast FPGA fabric the scaler core uses a separate clock domai...

Page 23: ...king Principles Hblank_in Input Vblank_in Input Frame_rst Signal Active_video_in Input General Input Handshaking Principles The input data is written into an internal double buffered line buffer Avail...

Page 24: ...a_in is required in the 4 2 0 case This must be asserted high on all lines for 4 2 2 but only for alternate lines for 4 2 0 as shown in Figure 4 2 When running the scaler using Live Mode you are likel...

Page 25: ...put must be tied to the horizontal blanking signal provided with the input video stream Also you may choose to use the inverse of hblank_in to create the active_video_in signal see the Active_video_in...

Page 26: ...n Input The active_video_in signal is generally used as an input data validation signal It must be provided into the scaler core on the same clock domain as the video data video_in_clk The timing of a...

Page 27: ...ept a new line of input data it asserts the rd_re signal high This signal will remain high for the duration of one line period determined by aperture_start_pixel and aperture_end_pixel The first left...

Page 28: ...gure 4 5 and data is driven out The video_out_almost_full input is provided to throttle the output from the scaler When this is asserted high for a number of line periods the line_request signal will...

Page 29: ...to another channel of the same video line The input buffering arrangement allows for the channels to be separated on a line basis The internal data path bit widths are shown in Figure 5 1 as implemen...

Page 30: ...is worth noting also that the Y and C operations do not work in synchrony Triple Engine for RGB 4 4 4 Processing For this architecture separate engines are used to process the three channels in paral...

Page 31: ...st case operational scenario When Auto Select is selected the GUI tries to establish what the user s worst case is from the following input parameters Input maximum rectangle size Output maximum recta...

Page 32: ...imilar calculation as above The user is advised to take a look at this value and may elect to force the GUI one way or the other This may be advisable in cases where for example a higher overhead per...

Page 33: ...s you to parameterize the scaler core in EDK The ports are driven by registers that sit on the AXI4 Lite The address is decoded in the wrapper A MicroBlaze processor software driver is provided in sou...

Page 34: ...t to which you intend to write The set may subsequently be used by controlling the h_coeff_set and v_coeff_set values start_hpa_y start_hpa_c start_vpa_y start_vpa_c These are the start phase controls...

Page 35: ...specify start_hpa_y start_hpa_c start_vpa_y start_vpa_c they are set internally to zero The control register is always set to 0x00000003 fixing the scaler in active mode General Purpose Processor GPP...

Page 36: ...abase to the drivers directory in your EDK project repository component_name drivers scaler_v3_01_a data scaler_v2_1_0 mdd scaler_v2_1_0 tcl example example c src Makefile xscaler c xscaler h xscaler_...

Page 37: ...Chapter 8 Coefficients for full details However the pCore wrapper and software driver mask you from the detail described Interrupts There are six interrupts 1 intr_output_frame_done Issued once per co...

Page 38: ...ture of the interrupt The interrupt registers are defined in Appendix B Programmer Guide A generic n peripheral system is shown in Figure 6 1 It shows the intended usage of interrupts in an EDK based...

Page 39: ...o important to understand how line 0 and pixel 0 are defined to ensure that these values are entered correctly Line 0 is defined as the first active line following a rising edge in active_video_in An...

Page 40: ...cale from a rectangle of size 80x60 starting at pixel line 20 32 Set the following Figure 7 3 shows the opening of an internal processing window signal t_verticalwindow with the preceding cropping set...

Page 41: ...ing a coe file multiple coefficient sets The number of phases for each set may also vary dependent upon the nature of the conversion and how you have elected to generate and partition the coefficients...

Page 42: ...icient Interface The scaler uses only one set of coefficients per frame period To change to a different set of stored coefficients for the next frame use the h_coeff_set and v_coeff_set dynamic regist...

Page 43: ...lk periods between write operations The guidelines are as follows The address coef_set_addr for all coefficients in one set must be written via the normal register interface coef_data_in delivers two...

Page 44: ...taps when coef_set_addr is updated Examples of Coefficient Set Generation and Loading As mentioned when data is fed in raster format coefficient 0 is applied to the lowest tap in the aperture for the...

Page 45: ...fficient file for download is shown in Table 8 3 The coefficients must be downloaded in the following order 1 Horizontal Luma always required 2 Horizontal Chroma required if not sharing Y and C coeffi...

Page 46: ...tion Ph Phase T Tap Load Sequence Number Value Calculation Ph Phase T Tap Phase 0 33 0x00000000 Ph0 T1 16 Ph0 T0 49 0x00000000 Ph0 T1 16 Ph0 T0 Phase 0 34 0x00000000 Ph0 T3 16 Ph0 T2 50 0x00000000 Ph0...

Page 47: ...Calculation Ph Phase T Tap Phase 0 1 0x00000000 Ph0 T1 16 Ph0 T0 33 0x00000000 Ph0 T1 16 Ph0 T0 Phase 0 2 0x00000000 Ph0 T3 16 Ph0 T2 34 0x00000000 Ph0 T3 16 Ph0 T2 3 0x00004000 Ph0 T5 16 Ph0 T4 35 0...

Page 48: ...ue Calculation Ph Phase T Tap Phase 0 65 0x00000000 Ph0 T1 16 Ph0 T0 97 0x00000000 Ph0 T1 16 Ph0 T0 Phase 0 66 0x00000000 Ph0 T3 16 Ph0 T2 98 0x00000000 Ph0 T3 16 Ph0 T2 67 0x00004000 Ph0 T5 16 Ph0 T4...

Page 49: ...y coef Phase 5 86 0x00000000 N A Dummy coef 118 0x00000000 N A Dummy coef 87 0x00000000 N A Dummy coef 119 0x00000000 N A Dummy coef 88 0x00000000 N A Dummy coef 120 0x00000000 N A Dummy coef Phase 6...

Page 50: ...h0 T5 16 Ph0 T4 4 0x00000000 Ph0 T7 16 Ph0 T6 24 0x00000000 Ph0 T7 16 Ph0 T6 5 0x00000000 0 16 Ph0 T8 25 0x00000000 0 16 Ph0 T8 Phase 1 6 0x0123FFB1 Ph1 T1 16 Ph1 T0 26 0x0123FFB1 Ph1 T1 16 Ph1 T0 Pha...

Page 51: ...4 Ph1 T1 16 Ph1 T2 67 0x3A810F04 Ph1 T1 16 Ph1 T2 48 0X0204F6FE Ph1 T1 16 Ph1 T4 68 0X0204F6FE Ph1 T1 16 Ph1 T4 49 0X0000FFA4 0 16 Ph1 T6 69 0X0000FFA4 0 16 Ph1 T6 50 0x00000000 N A dummy coef 70 0x00...

Page 52: ...Coefficients from this file can be extracted manually however it is important to know the format of this file All coefficients required for any conversion are provided with the SW Driver The filename...

Page 53: ...forth Format for coe Files The guidelines for creating a coe file are as follows Coefficients may be specified in either 16 bit binary form or signed decimal form First line of a 16 bit binary file mu...

Page 54: ...lowed by phase 1 etc The number of phases specified per bank in the coe file must be equal to Max_Phases even for filters that use fewer phases Set all coefficients in unused phases to 0 decimal or 00...

Page 55: ...0000000000000000 0 5 8 5199 0001010001001111 0 6 9 8167 0001111111100111 0 7 10 4457 0001000101101001 0 8 11 0 0000000000000000 0 9 12 616 1111110110011000 0 10 13 0 0000000000000000 0 11 14 85 00000...

Page 56: ...7 34 2060 0000100000001100 2 8 35 890 1111110010000110 2 9 36 366 1111111010010010 2 10 37 125 0000000001111101 2 11 38 53 0000000000110101 3 0 39 73 0000000001001001 3 1 40 72 0000000001001000 3 2 41...

Page 57: ...set of coefficients Table 8 11 coe File Example 2 Set Bank Phase Tap File line number Line Text N A 1 memory_initialization_radix 10 2 memory_initialization_vector 0 0 HY 0 0 3 0 0 0 HY 0 1 4 162 0 0...

Page 58: ...1 Separate H V Coefficients True Separate Y C Coefficients False 0 2 VY 3 11 146 28 0 3 VC 0 0 147 0 0 3 VC 0 1 148 162 0 3 VC 0 2 149 0 0 0 3 VC 3 0 183 73 0 3 VC 3 1 184 72 0 3 VC 3 0 3 VC 3 11 194...

Page 59: ...n_vector 0 H 0 0 3 104 0 H 0 1 4 1018 0 H 0 2 5 15364 0 H 0 3 6 106 0 H 1 0 7 240 0 H 1 1 8 4793 0 H 1 2 9 12022 0 H 1 3 10 191 0 H 2 0 11 282 0 H 2 1 12 8474 0 H 2 2 13 8474 0 H 2 3 14 282 0 H 3 0 15...

Page 60: ...ied coefficient bank is ready for reading Before changing the set and bank read address the user must set bit 3 of the control register to 0 Using the coef_set_bank_rd_addr the user provides a set num...

Page 61: ...FMax depends upon the selected device These factors may contribute to decisions made for configuring the scaler and its supporting system For example the user may decide to use the scaler in its dual...

Page 62: ...d frequency in this case often but not necessarily defined according to a known broadcast video format for example 1080i 60 720P CCIR601 etc The critical factors may be summarized as follows Processin...

Page 63: ...sPerEngine Max output_h_size SubjWidth OverHeadMult ProcessingOverheadPerComponent The CompsPerEngine and OverHeadMult values can be extracted from Table 9 2 NumEngines This is the number of engines u...

Page 64: ...culation MinF clk FLineIn x MaxClksTakenPerVAperture Also useful is the reciprocal relationship that defines the number of clk cycles available before the next line is written into the input line buff...

Page 65: ...00 Single engine implementation CyclesRequiredPerOutputLine 2 1920 150 approximately MaxVHoldsPerInputAperture round_up 1080 480 3 MaxClksTakenPerVAperture 3990 3 11970 MinF clk 30000 11970 359 1 MHz...

Page 66: ...ingle engine implementation CyclesPerOutputLine 2 1920 3 50 approximately MaxVHoldsPerInputAperture round_up 720 1080 1 MaxClksTakenPerVAperture 3990 1 3990 MinF clk 67500 3990 269 32 MHz Shrink facto...

Page 67: ...0 6667 0x155555 This conversion will work in Virtex 5 but not in Spartan 3A DSP since the MinF clk is greater than the Spartan 3A Fmax but less than the Virtex 5 Fmax as shown in Table 9 1 Memory Mode...

Page 68: ...essingOverhead For 4 2 2 dual engine CyclesPerOutputFrame Max output_h_size ProcessingOverheadPerLine 2 output_v_size input_h_size ProcessingOverheadPerLine 2 input_v_size FrameProcessingOverhead For...

Page 69: ...75 Horizontal scale ratio 1 5 FFrameIn 60 CyclesPerOutputFrame 1920 2 150 540 10000 approximately 2164600 MinF clk 60 x 2164600 129 87 MHz Shrink factor inputs hsf 220 x 1 1 5 0x0AAAAA vsf 220 x 1 0 8...

Page 70: ...70 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 9 Performance...

Page 71: ...start_line aperture_end_line aperture_start_pixel aperture_end_pixel output_h_size output_v_size hsf vsf These values are very significant and their usage is be referred to throughout this document X...

Page 72: ...e for Picture in Picture PinP HSF 220 x 1280 480 VSF 220 x 720 270 aperture_start_line 0 aperture_start_pixel 0 640 480 aperture_end_pixel 639 aperture_end_line 479 output_h_size 1280 output_y_size 72...

Page 73: ...X Ref Target Figure A 5 Figure A 5 Zoom Up scaling reading from External Memory HSF 220 x 480 1280 VSF 220 x 270 720 aperture_start_line 0 aperture_start_pixel 0 1280 480 270 720 aperture_end_pixel 4...

Page 74: ...74 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Appendix A Use Cases...

Page 75: ...hould be set to zero The number of taps is a compile time parameter for the IP core and needs to be known by the programmer to be able to load the coefficient tables correctly Register Definitions Not...

Page 76: ...ccumulator at rectangle top edge for luma 0x0034 start_vpa_y R W Fractional value used to initialize horizontal accumulator at rectangle left edge for chroma 0x0038 start_vpa_c R W Fractional value us...

Page 77: ...sing edge The registers that utilize this bit are 0x0010 through 0x0038 Usage This bit is cleared when the IP core next vblank happens Enable 0 Enable the Video Scaler core on the next video frame Tab...

Page 78: ...be polled by software for end for video scaler operation Usage This bit is cleared when any value is written to the register Table B 6 horizontal_shrink_factor Register 0x0010 horz_shrink_factor R W 3...

Page 79: ...f first pixel in line Table B 9 aperture_vert Register 0x001c aperture_vert R W 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2...

Page 80: ...ntal phases Table B 12 coeff_sets Register 0x0028 coeff_sets R W 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Reserve...

Page 81: ...1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Reserved start_vpa_y Name Bits Description Reserved 31 21 Reserved start_vpa_y 20 0 Fractional value used to initialize vertical accumulator for luma Ta...

Page 82: ...efficient set internal to the video scaler LSB aligned for coefficients less than 16 bits coef_value_N 15 0 Coefficient value N where N is index for the coefficient set Usage Each write to this regist...

Page 83: ...4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Reserved Coeff Readback Output Name Bits Description Coeff Readback Output 15 0 Coefficient readout from the scaler Table...

Page 84: ...flag indicating that the specified coefficient bank is ready for reading intr_reg_update_ done 5 Level sensitive issued during Vertical blanking when the register values have been transferred to the a...

Page 85: ...Model that generates coefficients Contact Xilinx support for information on how to obtain this C Model Refer to the Video Scaler Product Page for information about accessing the C Model Table B 26 In...

Page 86: ...Flow Chart Initialize Registers Set Load Coef Bank Load Coefs Set Active Coef Bank Enable Video Scaler Control 0 1 3 Disable Scaler Control O0 Start Scaling New Scale Factors New Coef Bank Initialize...

Page 87: ...Video Scaler v4 0 User Guide www xilinx com 87 UG805 March 1 2011 System Timing Diagram System Timing Diagram Figure B 0 System Timing Diagram...

Page 88: ...ure InstancePtr FirstLine LastLine define XScaler_GetVertAperture InstancePtr define XScaler_SetOutputSize InstancePtr Lines Pixels define XScaler_GetOutputSize InstancePtr define XScaler_SetNumPhases...

Page 89: ...ange for a new shrink factor are horz_shrink_factor vert_shrink_factor output_size Optionally these registers may also need to be modified depending on the input resolution and user preference apertur...

Page 90: ...bank every 50 frames Example Settings The following examples illustrate settings for different scale factors Pass Thru Table B 27 is an example of pass thru of a 1280 x 720 resolution image Table B 2...

Page 91: ...Address Name Decimal VAlue 0x0000 control 07 0x0010 hsf 2097152 0x0014 vsf 2097152 0x0018 aperture_start_pixel 0 0x0018 aperture_end_pixel 1279 0x001c aperture_start_line 0 0x001c aperture_end_line 71...

Page 92: ...92 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Appendix B Programmer Guide...

Page 93: ...caling the center of the 720P input image is cropped from memory and upscaled to 720P and displayed as a full 720P image on the output Operational clock frequencies are derived from the input clock Fi...

Page 94: ...ectionally used for writing input data into the memory Normally this should be configured as a write only core C_DMA_TYPE 0 However currently it is configured as a bidirectional core in this case C_DM...

Page 95: ...ach port includes a FIFO The FIFOs are configured to be 2048 pixels in length This is especially important for VDMA1 which handles video data to from the video scaler The video scaler arbitrates on a...

Page 96: ...cropping from memory you will be requesting a rectangle of a smaller width than the maximum line length Consequently the final lines may not be read from memory correctly resulting in some distortion...

Page 97: ...CE SPLB mb_plb BUS_INTERFACE XIL_VFBC vdma_1_XIL_VFBC BUS_INTERFACE XIL_RD_VDMA scaler_0_XIL_VDMA_SCALER_IN BUS_INTERFACE XIL_WD_VDMA scaler_0_XIL_VDMA_SCALER_OUT BUS_INTERFACE XIL_RD_SGENLOCK1 vdma_0...

Page 98: ...C_OUTPUT_MODE 1 BUS_INTERFACE XSVI_IN timebase_1_XSVI_OUT BUS_INTERFACE XSVI_OUT osd_0_XSVI_OUT BUS_INTERFACE XIL_RD0_VFBC osd_0_XIL_RD0_VFBC BUS_INTERFACE S_AXI axi_interconnect_0 PORT S_AXI_ACLK cl...

Page 99: ...0x00001fff BUS_INTERFACE SLMB dlmb BUS_INTERFACE BRAM_PORT dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE ilmb_cntlr PARAMETER HW_VER 2 10 b PARAMETER C_BASEADDR 0x00000000 PARAMETER C_HIGH...

Page 100: ...FBC2_RDWD_DATA_WIDTH 16 PARAMETER C_VFBC2_RDWD_FIFO_DEPTH 2048 PARAMETER C_PI2_WR_FIFO_TYPE SRL PARAMETER C_PI2_RD_FIFO_TYPE SRL PARAMETER C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT 20 PIM3 OSD1 Scaled Video Ou...

Page 101: ...Dcm_locked Dcm_all_locked PORT MB_Reset mb_reset PORT Bus_Struct_Reset sys_bus_reset PORT Peripheral_Reset sys_periph_reset PORT Interconnect_aresetn proc_sys_reset_0_Interconnect_aresetn END BEGIN xp...

Page 102: ..._BASEADDR 0xc3000000 PARAMETER C_SPLB_RNG1_HIGHADDR 0xc3ffffff PARAMETER C_SPLB_RNG1_NONSEC_SEC 1 PARAMETER C_SPLB_RNG1_CACHEABLE_BUFFERABLE 0 UART PARAMETER C_SPLB_RNG2_BASEADDR 0x83000000 PARAMETER...

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