Video Scaler v4.0 User Guide
www.xilinx.com
67
UG805 March 1, 2011
Memory Mode
Example 8:
Down-scaling 720P/60 YC4:2:2 to 640x480
45 kHz line rate
Vertical scale ratio = 0.6667
Horizontal scale ratio = 0.5
FLineIn = 45000
Single-engine implementation
CyclesRequiredPerOutputLine = 2*1280 + 150 (approximately)
MaxVHoldsPerInputAperture = round_up(480/720) = 1
MaxClksTakenPerVAperture = 2710 * 1 = 2710
MinF'clk' = 45000*2710 =
121.95 MHz
Shrink-factor inputs:
hsf=2
20
x (1/0.5) = 0x200000
vsf=2
20
x (1/0.6667) = 0x180000
This conversion will work in any of the supported devices and speed grades.
Example 9:
Converting 720P/60 YC4:2:2 to 1080i/60 (1920x540)
45 kHz line rate
Vertical scale ratio = 0.75
Horizontal scale ratio = 1.5
FLineIn = 45000
Single-engine implementation
CyclesRequiredPerOutputLine = 2*1920 + 150 (approximately)
MaxVHoldsPerInputAperture = round_up(540/720) = 1
MaxClksTakenPerVAperture = 3990 * 1 = 3990
MinF'clk' = 45000*3990 =
179.55 MHz
Shrink-factor inputs:
hsf=2
20
x (1/1.5) = 0x0AAAAA
vsf=2
20
x (1/0.6667) = 0x155555
This conversion will work in Virtex-5, but not in Spartan-3A DSP since the MinF'clk is
greater than the Spartan-3A Fmax, but less than the Virtex-5 Fmax, as shown in
Table 9-1
.
Memory Mode
Using an input frame buffer allows you to stretch the processing time over the entire frame
period (utilizing the available blanking periods). New input lines may be provided as the
internal phase-accumulator dictates, instead of the input timing signals.
The critical factors may be summarized as follows:
•
ProcessingOverheadPerLine
– The number of extraneous cycles needed by the scaler
to complete the generation of one output line, in addition to the actual processing
cycles. This is required due to filter latency and State-Machine initialization. For all
cases in this document, this has been approximated as
50 cycles
per component per
line.
•
FrameProcessingOverhead
– The number of extraneous cycles needed by the scaler
to complete the generation of one output
frame
, in addition to the actual processing
cycles. This is required mainly due to vertical filter latency. For all cases in this
document, this has been generally approximated as
10000 cycles per frame
.
Summary of Contents for LogiCORE IP
Page 1: ...LogiCORE IP Video Scaler v4 0 User Guide UG805 March 1 2011...
Page 6: ...Video Scaler v4 0 User Guide www xilinx com UG805 March 1 2011...
Page 14: ...14 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Preface About This Guide...
Page 18: ...18 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 1 Introduction...
Page 20: ...20 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 2 Overview...
Page 70: ...70 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 9 Performance...
Page 74: ...74 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Appendix A Use Cases...
Page 92: ...92 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Appendix B Programmer Guide...
