Xilinx LogiCORE IP, User Manual

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80 www.xilinx.com Video Scaler v4.0 User Guide
UG805 March 1, 2011
Appendix B: Programmer Guide
Reserved 15:11 Reserved
output_h_size 12:0 Number of pixels in output image
Table B-11: num_phases Register
0x0024 num_phases R/W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reserved num_v_phases num_h_phases
Name Bits Description
Reserved 31:15 Reserved
num_v_phases 14:8 Number of vertical phases
Reserved 7 Reserved
num_h_phases 6:0 Number of horizontal phases
Table B-12: coeff_sets Register
0x0028 coeff_sets R/W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reserved vcoeffset hcoeffset
Name Bits Description
Reserved 31:28 Reserved
vcoeffset 7:4 Active vertical coefficient set
hcoeffset 3:0 Active horizontal coefficient set
Table B-13: start_hpa_y Register
0x002c start_hpa_y R/W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reserved start_hpa_y
Name Bits Description
Reserved 31:21 Reserved
start_hpa_y 20:0
Fractional value used to initialize horizontal accumulator
for luma
Table B-10: output_size Register