Xilinx LogiCORE IP, User Manual

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Video Scaler v4.0 User Guide www.xilinx.com 75
UG805 March 1, 2011
Appendix B
Programmer Guide
Introduction
This appendix provides a description of how to program and control the data flow for the
video scaler hardware pCore. The information is sufficient for the development of a
software driver (API) for use in application software for applications such as video
conferencing and video analytics.
Note:
A software driver is provided with the pCore so that you do not have to develop a software API
as described here.
Conventions
Reserved locations in the registers will be ignored by the hardware and can be written by
software with any value. Therefore the software does not need to zero or mask bits.
Unused coefficients should be set to zero. The number of taps is a compile time parameter
for the IP core and needs to be known by the programmer to be able to load the coefficient
tables correctly.
Register Definitions
Note:
All registers default to 0x00000000 on power-up or software reset.
Table B-1: Video Scaler Registers Overview
Address Name Read/Write Description
0x0000 control R/W General control register
0x0004 status R General readable status register
0x0008 status_error R General readable status register for errors
0x000c status_done R/W General read register for status done
0x0010 horz_shrink_factor R/W Horizontal Shrink Factor
0x0014 vert_shrink_factor R/W Vertical Shrink Factor
0x0018 aperture_horz R/W
aperture_start_pixel: Location of first subject pixel in input line,
relative to first active pixel in that line
aperture_end_pixel: Location of final subject pixel in input line,
relative to first active pixel in that line