Video Scaler v4.0 User Guide
www.xilinx.com
25
UG805 March 1, 2011
Data Source: Live Video
Hblank_in Input
The horizontal blanking input signal
hblank_in
is generally used as a line-based reset. It
must be provided to the scaler core in the same clock domain as the video data
(
video_in_clk
).
The
hblank_in
signal is used to perform the following operations:
•
Reset an internal input pixel counter.
•
Reset the internal input side line buffer write-address pointer.
•
Increment the input line counter (rising edge of
hblank_in
).
•
Decode the input line count during active data period to open and close an internal
processing “window.”
•
Decode the input line count to create a delayed internal frame-based reset signal
(
frame_rst
) during
vblank_in
. The line-number is specified in the CORE
Generator GUI (
Frame Reset line Number
).
The timing of
hblank_in
must satisfy the following criteria:
•
It must be low for the active-data duration of the input line.
•
It must be high for a period
greater than or equal to 100
video_in_clk
-cycles
in
duration, once per line. This allows the scaler time to handle inherent line-based
latency in the filters.
•
It must be low for a period
greater than or equal to 32
video_in_clk
-cycles
in
duration, once per line.
The
hblank_in
input must be tied to the horizontal blanking signal provided with the
input video stream. Also, you may choose to use the inverse of
hblank_in
to create the
active_video_in
signal (see the
Active_video_in Input
section).
Vblank_in Input
The vertical blanking input signal
vblank_in
is generally used as a frame-based reset. It
must be provided into the scaler core on the same clock domain as the video data
(
video_in_clk
).
The
vblank_in
signal is used to perform the following operations:
•
Reset input line counter (both edges).
•
Generate internal frame-based reset signal (
frame_rst
) during vertical blanking.
In Live Video mode,
Frame Reset Line Number
must be set to a value that is lower than
the number of line periods for which
vblank_in
remains high between frames. To
characterize this further,
hblank_in
must transition high a larger number of times than
Frame Reset Line Number
while
vblank_in
is high.
The
vblank_in
input must be tied to the vertical blanking signal provided with the input
video stream.
Frame_rst Signal
To maximize robustness of the scaler core, it is preferable to reset internal state-machines,
FIFOs and other processes once per frame. Owing to inherent multi-line period latency in
the system, it is not possible to use the
vbank_in
for this purpose. During
vblank_in
,
hblank_in
must continue to be active (as per most video formats).
Frame_rst
is
generated when the number of
hblank_in
pulses equals
Frame Reset Line Number
Summary of Contents for LogiCORE IP
Page 1: ...LogiCORE IP Video Scaler v4 0 User Guide UG805 March 1 2011...
Page 6: ...Video Scaler v4 0 User Guide www xilinx com UG805 March 1 2011...
Page 14: ...14 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Preface About This Guide...
Page 18: ...18 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 1 Introduction...
Page 20: ...20 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 2 Overview...
Page 70: ...70 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 9 Performance...
Page 74: ...74 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Appendix A Use Cases...
Page 92: ...92 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Appendix B Programmer Guide...
