Xilinx LogiCORE IP, User Manual

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Video Scaler v4.0 User Guide www.xilinx.com 61
UG805 March 1, 2011
Chapter 9
Performance
The target maximum clock frequencies for all scaler input clocks are shown in Table 9-1 .
It is very important to ensure that the clock rate available supports worst-case conversions.
This chapter includes detailed information and examples for worst-case scenarios.
Every user of the Xilinx Video Scaler should have a worst-case scenario in mind. The
factors that may contribute to this scenario include:
• Maximum line length to be handled in the system (into and out from the scaler)
• Maximum number of lines per frame (in and out)
• Maximum frame refresh rate
• Chroma format (4:4:4, 4:2:2, or 4:2:0)
• Clock FMax (depends upon the selected device)
These factors may contribute to decisions made for configuring the scaler and its
supporting system. For example, the user may decide to use the scaler in its dual-engine
parallel Y/C configuration to achieve the scale factor and frame rate desired. Using a dual-
engine scaler allows the scaler to process more data per clock cycle at the cost of an
increased resource usage. He may also elect to change speed-grade or even device family
dependent upon his findings.
The size of the scaler implementation is determined by the number of taps and number of
phases in the filter and the number of engines. The number of taps and number of phases
do not impact the clock frequency.
Table 9-1: Target Maximum Clock Frequencies
Family Speed grade FMax (MHz)
Virtex-5 -1 225
-2 250
-3 275
Virtex-6 -1 250
-2 280
Spartan-6 -2 150
-3 160
Spartan-3A DSP -4 150
-5 160