DRAM Write Tim ing
This op tion con trols the write tim ing to the DRAM ar ray. The avail able op tions are shown here :
slow
nor mal - de fault
fast
fast est
SRAM Read Tim ing
This op tion al lows for se lec tion of the tim ing pat terns used to ac cess the Cache RAM. The avail able
choices are :
2- 1- 1-1
3- 1- 1-1 De fault
3- 2- 2-2
4- 2- 2-2
SRAM Write Tim ing
This op tion con trols the number of wait- states to be in serted dur ing cache write op era tions. The
choices are :
0 Wait
1 Wait De fault
ISA I/O Re cov ery
The CPU and lo cal bus are much faster than the stan dard for the ISA bus. Se lect ing en abled for this
op tion al lows ad di tional time for I/O de vices to re spond to the sys tem. The de fault is dis abled.
Fast Back- To- Back
When en abled, con secu tive write cy cles tar geted to the same slave be come fast back- to- back on the
PCI bus. The de fault set ting is dis abled.
On Chip Lo cal Bus IDE
This op tion when en abled al lows us age of the on board PCI Bus IDE con trol ler. The de fault is en -
abled.
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OPERATIONS MANUAL LBC-Plus
991206
WinSystems - "The Embedded Systems Authority"
