UTAH SCIENTIFIC Utah-400 iP, System Setup And Operations

Page: 126 / 146

The Debug Port
B-4
The Debug Port
Using the Debug Port
The debug port is the RJ-45 female connector labeled J1, located at the center of the cross-
point. Its capabilities include:
•
System Power Up Display
•
Main Menu Display.
•
Verifying the FPGA Memory Status .
•
Verifying the Software Version .
•
Checking the Router Crosspoint Status to verify switching.
•
Checking the I / O Card Information .
•
Checking the Hardware Status .
Only the “Active” FPGA Control board will be read by the Debug Port. By pressing the “Reset”
button on the currently active FPGA board, the control should be transferred to the inactive
board.
If both FPGA’s are to be checked, be sure to press the “Reset” button after reading the first
board.