SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08
Objective Specification
Design-in
Page 118 of 188
If a 1.8 V application processor is used, the circuit that should be implemented as described in Figure 64:
TxD
Application Processor
(1.8V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
SARA-G3 / SARA-U2
(1.8V DCE)
12
TXD
9
DTR
13
RXD
10
RTS
11
CTS
6
DSR
7
RI
8
DCD
GND
0
Ω
TP
0
Ω
TP
0
Ω
TP
TP
Figure 64: UART interface application circuit with partial V.24 link (3-wire) in the DTE/DCE serial communication (1.8 V DTE)
If a 3.0 V Application Processor is used, appropriate unidirectional voltage translators must be provided using the
module
V_INT
output as 1.8 V supply, as described in Figure 65.
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
DTR
DSR
RI
DCD
GND
SARA-G3 / SARA-U2
(1.8V DCE)
12
TXD
9
DTR
13
RXD
6
DSR
7
RI
8
DCD
GND
1V8
B1
A1
GND
U1
VCCB
VCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR1
DIR2
OE
VCC
B2
A2
RTS
CTS
10
RTS
11
CTS
TP
0
Ω
TP
0
Ω
TP
0
Ω
TP
TP
Figure 65: UART interface application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE)
Reference
Description
Part Number - Manufacturer
C1, C2
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1
Unidirectional Voltage Translator
SN74AVC2T245 - Texas Instruments
Table 34: Component for UART application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE)
If only
TXD
and
RXD
lines are provided, as described in Figure 64 or in Figure 65, and HW flow-control is
disabled (AT&K0), the power saving must be enabled in this way:
AT+UPSV=1: the module automatically enters the low power idle-mode whenever possible and the UART
interface is periodically enabled, as described in section 1.9.1.4, reaching low current consumption.
With this configuration, when the module is in idle-mode, the UART is re-enabled 20 ms after the first data
reception, and the recognition of subsequent characters is guaranteed until the module is in active-mode.
If only
TXD
and
RXD
lines are provided, data delivered by the DTE can be lost with these settings:
o
HW flow-control enabled in the module (AT&K3, that is the default setting)
o
Module power saving enabled by AT+UPSV=1
o
HW flow-control disabled in the DTE
In this case the first character sent when the module is in idle-mode will be a wake-up character and will
not be a valid communication character (see section 1.9.1.4 for the complete description).
