SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08
Objective Specification
Design-in
Page 151 of 188
2.15.3
Schematic for SARA-U2 series modules integration
Figure 86 is an example of a schematic diagram where a SARA-U2 module is integrated into an application
board, using all the available interfaces and functions of the module.
TXD
RXD
RTS
CTS
DTR
DSR
RI
DCD
GND
12
TXD
9
DTR
13
RXD
10
RTS
11
CTS
6
DSR
7
RI
8
DCD
GND
3V8
GND
330µF
10nF
100nF
56pF
SARA-U2 series
52
VCC
53
VCC
51
VCC
+
100µF
2
V_BCKP
GND
GND
GND
RTC
back-up
1.8V DTE
USB 2.0 Host
16
GPIO1
3V8
Network
Indicator
18
RESET_N
Application
Processor
Open
Drain
Output
15
PWR_ON
100k
Ω
Open
Drain
Output
D+
D-
29
USB_D+
28
USB_D-
u-blox 1.8 V
GNSS Receiver
4.7k
OUT
IN
GND
LDO Regulator
SHDN
SDA
SCL
4.7k
3V8
1V8_GPS
SDA2
SCL2
GPIO3
GPIO4
TxD1
EXTINT0
26
27
24
25
47k
VCC
GPIO2
23
RSVD
RSVD
RSVD
RSVD
46
47
48
49
15pF
33
RSVD
31
RSVD
47pF
SIM Card Holder
CCVCC (C1)
CCVPP (C6)
CCIO (C7)
CCCLK (C3)
CCRST (C2)
GND (C5)
47pF 47pF
100nF
41
VSIM
39
SIM_IO
38
SIM_CLK
40
SIM_RST
47pF
SW1
SW2
4
V_INT
42
SIM_DET
470k
ESD ESD ESD ESD ESD ESD
56
ANT
62
ANT_DET
10k
82nH
33pF
Connector
27pF
ESD
External
Antenna
V_BCKP
1k
TP
TP
TP
0
Ω
0
Ω
TP
TP
0
Ω
0
Ω
TP
TP
V_INT
BCLK
LRCLK
Audio Codec
MAX9860
SDIN
SDOUT
SDA
SCL
36
I2S_CLK
34
I2S_WA
35
I2S_TXD
37
I2S_RXD
19
CODEC_CLK
MCLK
IRQn
10k
10µF
1µF
100nF
VDD
SPK
OUTP
OUTN
MIC
MICBIAS
1µF
2.2k
1µF
1µF
MICLN
MICLP
MICGND
2.2k
ESD ESD
V_INT
10nF
10nF
EMI
EMI
27pF
27pF
10nF
EMI
EMI
ESD ESD
27pF
27pF
10nF
V_INT
RSVD
RSVD
44
45
VBUS
17
VUSB_DET
100nF
0
Ω
15pF
39nH
Figure 86: Example of schematic diagram to integrate SARA-U2 module in an application board, using all the interfaces
For a complete schematic example including all SARA-G3 and SARA-U2 series modules see Figure 94.
