SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08
Objective Specification
System description
Page 60 of 188
1.10.2.1
I
2
S interface – PCM mode
Main features of the I
2
S interface in PCM mode (configurable by AT+UI2S command):
I
2
S runs in PCM – short alignment mode
I
2
S word alignment signal is configured by the <I2S_sample_rate> parameter
I
2
S word alignment is set high for 1 or 2 clock cycles for the synchronization, and then is set low for 16 clock
cycles of sample width. The frame length, according to the length of the high pulse for the synchronization,
can be 1 + 16 = 17 bits or 2 + 16 = 18 bits
I
2
S clock frequency depends on the frame length and the sample rate. It can be 17 x <I2S_sample_rate> or
18 x <I2S_sample_rate>
I
2
S transmit and I
2
S receive data are 16 bit words long with the same sampling rate as I
2
S word alignment,
mono. Data is in 2’s complement notation. MSB is transmitted first
When I
2
S word alignment toggles high, the first synchronization bit is always low. Second synchronization
bit (present only in case of 2 bit long I
2
S word alignment configuration) is MSB of the transmitted word (MSB
is transmitted twice in this case)
I
2
S transmit data changes on I
2
S clock rising edge, I
2
S receive data changes on I
2
S clock falling edge
1.10.2.2
I
2
S interface – Normal I
2
S mode
Normal I
2
S supports:
16 bits word
Mono interface
Sample rate: <I2S_sample_rate> parameter
Main features of I
2
S interface in normal I
2
S mode (configurable by AT+UI2S command):
I
2
S runs in normal I
2
S – long alignment mode
I
2
S word alignment signal always runs at the <I2S_sample_rate> and synchronizes 2 channels (timeslots on
word alignment high, word alignment low)
I
2
S transmit data is composed of 16 bit words, dual mono (the words are written on both channels). Data
are in 2’s complement notation. MSB is transmitted first. The bits are written on I
2
S clock rising or falling
edge (configurable)
I
2
S receive data is read as 16 bit words, mono (words are read only on the timeslot with WA high). Data is
read in 2’s complement notation. MSB is read first. The bits are read on the I
2
S clock edge opposite to I
2
S
transmit data writing edge (configurable)
I
2
S clock frequency is 16 bits x 2 channels x <I2S_sample_rate>
The modes are configurable through a specific AT command (refer to the related section in the
u-blox AT
[3], +UI2S AT command) and the following parameters can be set:
MSB can be 1 bit delayed or non-delayed on I
2
S word alignment edge
I
2
S transmit data can change on rising or falling edge of I
2
S clock signal
I
2
S receive data are read on the opposite front of I
2
S clock signal
