SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08
Objective Specification
Design-in
Page 81 of 188
2
Design-in
2.1
Overview
For an optimal integration of SARA-G3 and SARA-U2 series modules in the final application board follow the
design guidelines stated in this section.
Every application circuit must be properly designed to guarantee the correct functionality of the related interface,
however a number of points require higher attention during the design of the application device.
The following list provides a ranking of importance in the application design, starting from the highest relevance:
1.
Module antenna connection:
ANT
and
ANT_DET
pins. Antenna circuit directly affects the RF compliance of
the device integrating a SARA-G3 and SARA-U2 series module with the applicable certification schemes.
Very carefully follow the suggestions provided in section 2.4 for schematic and layout design.
2.
Module supply:
VCC
and
GND
pins. The supply circuit affects the RF compliance of the device integrating a
SARA-G3 and SARA-U2 series module with applicable certification schemes as well as antenna circuit design.
Very carefully follow the suggestions provided in section 2.2.1 for schematic and layout design.
3.
USB interface:
USB_D+
,
USB_D-
and
VUSB_DET
pins. Accurate design is required to guarantee USB 2.0
high-speed interface functionality. Carefully follow the suggestions provided in the related section 2.6.1 for
schematic and layout design.
4.
SIM interface:
VSIM
,
SIM_CLK
,
SIM_IO
,
SIM_RST
,
SIM_DET
pins. Accurate design is required to guarantee
SIM card functionality and compliance with applicable conformance standards, reducing also the risk of RF
coupling. Carefully follow the suggestions provided in section 2.5 for schematic and layout design.
5.
System functions:
RESET_N
,
PWR_ON
pins. Accurate design is required to guarantee that the voltage level
is well defined during operation. Carefully follow the suggestions provided in section 2.3 for schematic and
layout design.
6.
Analog audio interface:
MIC_BIAS
,
MIC_GND
,
MIC_P
,
MIC_N
uplink and
SPK_P
,
SPK_N
downlink pins.
Accurate design is required to obtain clear and high quality audio reducing the risk of noise from audio lines
due to both supply burst noise coupling and RF detection. Carefully follow the suggestions provided in
section 2.7.1 for schematic and layout design.
7.
Other digital interfaces: UART and auxiliary UART interfaces, DDC I
2
C-compatible interface, digital audio
interface and GPIOs. Accurate design is required to guarantee proper functionality and reduce the risk of
digital data frequency harmonics coupling. Follow the suggestions provided in sections 2.6.1, 2.6.2, 2.6.4,
2.7.2 and 2.8 for schematic and layout design.
8.
32 kHz signal: the
EXT32K
input pin and the
32K_OUT
output pin of SARA-G300 and SARA-G310 modules
require accurate layout design as it may affect the stability of the RTC reference. Follow the suggestions
provided in section 2.3.3 for schematic and layout design.
9.
Other supplies: the
V_BCKP
RTC supply input/output and the
V_INT
digital interfaces supply output.
Accurate design is required to guarantee proper functionality. Follow the suggestions provided in sections
2.2.2 and 2.2.3 for schematic and layout design.
