1
1
2
2
3
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4
4
D
D
C
C
B
B
A
A
Date:
Page
20
of
32
Number:
Title:
TEF1001_FPGA_MGT_BANKS
01
Rev.
A4
Copyright:
Trenz Electronic GmbH
FPGA_MGT_BANKS.SchDoc
Filename:
2017-02-14
Default
TEF1001
MGTAVTT_FPGA
MGTAVCC_FPGA
MGTVCCAUX_FPGA
DP0_C2M_P
DP1_C2M_P
DP2_C2M_P
DP3_C2M_P
DP0_C2M_N
DP1_C2M_N
DP2_C2M_N
DP3_C2M_N
DP0_M2C_P
DP1_M2C_P
DP2_M2C_P
DP3_M2C_P
DP0_M2C_N
DP1_M2C_N
DP2_M2C_N
DP3_M2C_N
PER0_P
PER1_P
PER2_P
PER3_P
PER0_N
PER1_N
PER2_N
PER3_N
PET0_P
PET1_P
PET2_P
PET3_P
PET0_N
PET1_N
PET2_N
PET3_N
i
PCIE
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GBTCLK1_M2C_P
GBTCLK1_M2C_N
6.3V
X5R
C51
4.7µF
GND
6.3V X5R
C53
4.7µF
GND
6.3V
X5R
C55
4.7µF
GND
6.3V X5R
C54
4.7µF
GND
6.3V
X5R
C56
4.7µF
GND
6.3V
X5R
C52
4.7µF
GND
i
PCIE
1%
R54
100R
MGTAVTT_FPGA
MGTXTXN3_115
H1
MGTXTXP3_115
H2
MGTXTXN2_115
K1
MGTXTXP2_115
K2
MGTXTXN1_115
M1
MGTXTXP1_115
M2
MGTXTXN0_115
P1
MGTXTXP0_115
P2
MGTXRXN3_115
J3
MGTXRXP3_115
J4
MGTXRXN2_115
L3
MGTXRXP2_115
L4
MGTXRXN1_115
N3
MGTXRXP1_115
N4
MGTXRXN0_115
R3
MGTXRXP0_115
R4
MGTREFCLK1N_115
K5
MGTREFCLK1P_115
K6
MGTREFCLK0N_115
H5
MGTREFCLK0P_115
H6
MGTRREF_115
M6
MGTAVTTRCAL_115
M5
MGTXTXN3_116
A3
MGTXTXP3_116
A4
MGTXTXN2_116
B1
MGTXTXP2_116
B2
MGTXTXN1_116
D1
MGTXTXP1_116
D2
MGTXTXN0_116
F1
MGTXTXP0_116
F2
MGTXRXN3_116
B5
MGTXRXP3_116
B6
MGTXRXN2_116
C3
MGTXRXP2_116
C4
MGTXRXN1_116
E3
MGTXRXP1_116
E4
MGTXRXN0_116
G3
MGTXRXP0_116
G4
MGTREFCLK1N_116
F5
MGTREFCLK1P_116
F6
MGTREFCLK0N_116
D5
MGTREFCLK0P_116
D6
MGTVCCAUX
N6
MGTAVTT
M3
MGTAVTT
L2
MGTAVTT
H3
MGTAVTT
G2
MGTAVTT
D3
MGTAVTT
C2
MGTAVTT
B3
MGTAVCC
L6
MGTAVCC
J6
MGTAVCC
G6
MGTAVCC
E6
MGTAVCC
C6
U6J
XC7K160T-2FBG676I
i PCIE
PCIE_CLK_P
PCIE_CLK_N
MGTCLK_5338_P
MGTCLK_5338_N
