Trenz Electronic TEF1001, Schematics

Page: 5 / 32

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Date: Page 5 of 32
Number:
Title:
TEF1001 - CONN
01
Rev.
A4
Copyright: Trenz Electronic GmbH
CONN.SchDoc
Filename:
2017-02-14
Default
TEF1001
U_PCIE_CONN
PCIE_CONN.SchDoc
GND
FPGA_JTAG_TDI
FPGA_JTAG_TDO
FPGA_JTAG_TCK
FPGA_JTAG_TMS
FPGA JTAG CONNECTOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J9
WANNE2mm2R-14
1V8
CPLD JTAG CONNECTOR
1
2
3
4
5
6
J8
Stiftleiste versetzt 1-reihig, 6pol.
GND
CPLD_JTAG_TDI
CPLD_JTAG_TDO
CPLD_JTAG_TCK
CPLD_JTAG_TMS
3V3
1
2
3
4
J4
Stiftleiste 4 Pol. 2,54mm
FAN 2
FAN 1
GND GND
F1SENSE
F1PWM
1
2
J6
Wire to board, 2 pol. header
L4
MPZ1608S221A
L21
MPZ1608S221A
12V
1%
R24
100R
1%
R25
100R
1%
R26
10K7
5V
3V3
JX1
Wire to board, 2 pol. housing
JCT1
Crimp Terminal 4809, 22-30 AWG
JCT2
Crimp Terminal 4809, 22-30 AWG
1
J10
JUMPER2.54-3
LTM I2C CONNECTOR
GND
LTM_SDA
LTM_SCL
U_FMC
FMC.SchDoc