1
1
2
2
3
3
4
4
D
D
C
C
B
B
A
A
Date:
Page
13
of
32
Number:
Title:
TEF1001 - FPGA_BANK_14
01
Rev.
A4
Copyright:
Trenz Electronic GmbH
FPGA_BANK_14.SchDoc
Filename:
2017-02-14
Default
TEF1001
1%
R29
1K13
GND
GND
FLASH_QSPI_D00
FLASH_QSPI_D01
FLASH_QSPI_D02
FLASH_QSPI_D03
FLASH_QSPI_CS
R28
4K7
i
SPIFLASH
PUDC_B
1%
R12
4K7
1%
R11
4K7
6.3V
X5R
C45
470nF
GND
6.3V
X5R
C44
47µF
GND
U12
N25Q256A11ESF40G
FPGA_CFG_CCLK
FLASH_QSPI_CS
FLASH_QSPI_D00
FLASH_QSPI_D01
FLASH_QSPI_D02
FLASH_QSPI_D03
1V8
1V8
1V8
LOW ENABLE PULLUP !!!!
1%
R82
1K13
1V8
BR0 BR1 BR2 BR3
--------------------------------------
1 0 0 0 | REV01
GND
GND
1V8
Board Revisions
BR0
BR1
BR2
BR3
U6C
XC7K160T-2FBG676I
GND
CLK0_P
CLK1_P
CLK0_N
CLK1_N
CLK2_N
CLK2_P
FPGA_IIC_SDA
FPGA_IIC_SCL
FPGA_IIC_OE
1%
R85
4K7
1%
R86
4K7
1%
R87
4K7
FPGA_IIC_SDA
FPGA_IIC_SCL
FPGA_IIC_OE
1V8
1%
R72
0R
1%
R73
100K
GND
FEX4
FEX5
FEX8
FEX9
FEX6
FEX7
FEX10
FEX11
FEX0
FEX1
FEX3
FEX2
FEX_DIR
R62
100R
Remove R if not needed
R63
100R
Remove R if not needed
R64
100R
Remove R if not needed
CLK0_P
CLK1_P
CLK0_N
CLK1_N
CLK2_N
CLK2_P