1
1
2
2
3
3
4
4
D
D
C
C
B
B
A
A
Date:
Page
18
of
32
Number:
Title:
TEF1001 - FPGA_BANK_33
01
Rev.
A4
Copyright:
Trenz Electronic GmbH
FPGA_BANK_33.SchDoc
Filename:
2017-02-14
Default
TEF1001
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
DDR3_A13
DDR3_A14
DDR3_A15
DDR3_CB0
DDR3_CB1
DDR3_CB2
DDR3_CB3
DDR3_CB4
DDR3_CB5
DDR3_CB6
DDR3_CB7
DDR3_DQS8_P
DDR3_DQS8_N
DDR3_DM8
VREF_VTT
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_CK0_P
DDR3_CK0_N
DDR3_CK1_P
DDR3_CK1_N
DDR3_CKE0
DDR3_CKE1
DDR3_RASN
DDR3_CASN
DDR3_WEN
DDR3_ODT0
DDR3_ODT1
DDR3_S0N
DDR3_S1N
VRN_33
1V5
1%
R21
90R9
1%
R22
90R9
1V5
GND
6.3V
X5R
C91
47µF
GND
ClassName: Bank33
VREF_VTT
16V
X7R
C101
10nF
GND
DDR3_CLK_P
DDR3_CLK_N
VRP_33
AE11
AD11
AC11
AB11
U6G
XC7K160T-2FBG676I
ClassName: CLK_DDR3
Fixed
Fixed
