1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
A
Date:
Page
32
of
32
Number:
Title:
TEF1001 - Power Ens_PGs_COMMs
01
Rev.
A4
Copyright:
Trenz Electronic GmbH
POWER_ENs_PGs OVERVIEW.SchDoc
Filename:
2017-02-14
Default
TEF1001
1.8V
TPS62170DSG
FMC
CONNECTOR
4V
3V3FMC
CPLD JTAG
EN6347QI
FPGA - BANK_16 (HBxx)
1
2
V
4V
FMC_VADJ
EN5365QI
Default: ??
12V
3V3
DSC1123DL5-200.0000 (DDR3 CLK)
SiT8208AI-G1-33S-25.000000 (OSCILATOR)
TPS79901DRV
MGTVCCAUX
DDR3 - VDDSPD
3V3
3V3
FAN 1
12V
LTM4676EY
LTM4676EY
12V
12V
4V / 13A
1V5 / 13A
1V / 26A
FPGA - MGTAVTT
TPS74401RGW
FPGA - MGTAVCC
TPS74401RGW
VIN
BIAS
VIN
BIAS
1.0V
1.2V
FPGA JTAG
FPGA - BANK_14
EN6347QI
4V
FPGA - VCCBRAM
1V
FPGA - BANK_0
N25Q256A11E (FLASH MEM)
CPLD - VCCIO3
SI5338A (CLKS GEN)
TPS62170DSG
12V
5V
FAN 2
1V8
TPS51206DSQ
4V
DDR3 VDD
12V (from PCIe 6-Pin Connector (J5))
3V3FMC
VIO_B_FMC
3V3
CPLD - VCC+VCCIO2
1V5
4V
FPGA - VCCAUX_IO
FPGA - BANK_12 (HAxx)
FPGA - BANK_13 (LAxx)
FPGA - BANK_15 (LAxx)
FMC_VADJ
1V5
4V
1V5
1V5
FPGA - BANK_32
FPGA - BANK_33
FPGA - BANK_34
4V
1V5
DDR3 - VTT
FPGA - VREF VTT
750mV
750mV
EN
PG
EN
PG
(TO CPLD)
(FROM CPLD)
EN
PG
(TO CPLD)
(FROM CPLD)
EN
PG
(TO CPLD)
(FROM CPLD)
3V3 / 500mA
5V / 500mA
1V8 / 4A
1.8V / 200mA
VADJ / 6A
3V3 / 4A
750mV / 10mA
1.0V / 3A
1.2V / 3A
750mV / 2A
