1
1
2
2
3
3
4
4
D
D
C
C
B
B
A
A
Date:
Page
19
of
32
Number:
Title:
TEF1001 - FPGA_BANK_34
01
Rev.
A4
Copyright:
Trenz Electronic GmbH
FPGA_BANK_34.SchDoc
Filename:
2017-02-14
Default
TEF1001
DDR3_D0
DDR3_D1
DDR3_D2
DDR3_D3
DDR3_D4
DDR3_D5
DDR3_D6
DDR3_D7
DDR3_D8
DDR3_D9
DDR3_D10
DDR3_D11
DDR3_D12
DDR3_D13
DDR3_D14
DDR3_D15
DDR3_D16
DDR3_D17
DDR3_D19
DDR3_D18
DDR3_D20
DDR3_D21
DDR3_D22
DDR3_D23
DDR3_D24
DDR3_D25
DDR3_D26
DDR3_D27
DDR3_D28
DDR3_D29
DDR3_D30
DDR3_D31
VREF_VTT
VREF_VTT
DDR3_DQS0_P
DDR3_DQS0_N
DDR3_DQS1_P
DDR3_DQS1_N
DDR3_DQS2_P
DDR3_DQS2_N
DDR3_DQS3_P
DDR3_DQS3_N
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
1V5
6.3V
X5R
C48
47µF
GND
16V
X7R
C99
10nF
GND
DDR3_EVENTN
U6H
XC7K160T-2FBG676I
ClassName: Bank34
1V5
GND
VRN_34
VRP_34
