NTM6900 / WTM7026 Technical Reference
PCI Express Reference
Chapter 2 PCI Express® and PCI Option Card Slots
Introduction
PCI Express®
is a high-speed, high-bandwidth interface with multiple channels (lanes) bundled together
with each lane using full-duplex, serial data transfers with high clock frequencies.
The PCI Express architecture is based on the conventional PCI addressing model, but improves upon it by
providing a high-performance physical interface and enhanced capabilities. Whereas the PCI bus
architecture provided parallel communication between a processor board and backplane, the PCI Express
protocol provides high-speed serial data transfer, which allows for higher clock speeds. The same data rate
is available in both directions simultaneously, effectively reducing bottlenecks between the motherboard’s
logic components and PCI Express option card slots.
PCI Express option cards may require updated device drivers. Most operating systems that support legacy
PCI cards will also support PCI Express cards without modification. Because of this interface design, a
single PCI card and multiple PCI Express option cards can co-exist in the same system.
PCI Express serial interface connectors have lower pin counts than PCI parallel bus connectors. The PCIe
connectors are physically different, based on the number of lanes in the connector.
PCI Express Links
Several PCI Express channels (lanes) are bundled together for each PCIe option card slot. A link is a
collection of one or more PCIe lanes. A basic full-duplex link consists of two dedicated lanes for receiving
data and two dedicated lanes for transmitting data. PCI Express supports scalable link widths in 1-, 4-, 8-
and 16-lane configurations, generally referred to as x1, x4, x8 and x16 slots. A PCI Express x4 slot with a
PCIe 1.1 interface implementation indicates that the slot has four PCIe lanes, which gives the slot a
bandwidth of 250MB/s in each direction per lane. Unlike PCI parallel buses, there are no additional
devices sharing a serial PCI Express interface. Since there are no additional devices competing for
bandwidth; the effective bandwidth is counted in both directions and results in 500MB/s (full-duplex) per
lane or 2GB/s for the x4 PCIe 1.1 card slot. If an option card with a PCI Express 2.0 interface is installed
into the x4 PCIe5 or PCIe7 motherboard slots, then this effective full-duplex bandwidth doubles to 4GB/s.
The link configuration of the motherboard’s PCI Express links is determined by specific interface
specification of the PCI Express option card. In PCI Express Gen 1.1 and Gen 2.0 bandwidths for the PCIe
links are deter-mined by the link width multiplied by 250MB/s and 500MB/s, as follows:
Card Slot
Size
PCIe 1.1
Bandwidth
PCIe 1.1 Full-Duplex
Bandwidth
PCIe 2.0
Bandwidth
PCIe 2.0 Full-Duplex
Bandwidth
x1
250MB/s 500MB/s
500MB/s 1GB/s
x4
1GB/s 2GB/s
2GB/s 4GB/s
x8
2GB/s 4GB/s
4GB/s 8GB/s
Scalability is a core feature of PCI Express. An option card with a higher number of PCIe lanes will not
function in a mechanical slot set-up with a lower number of lanes available (e.g., a x8 board in a x4
mechanical slot) because the connectors are mechanically incompatible. However, the reverse
configuration will function on the motherboard without any electrical issues. A board with a lower number
of lanes can be placed into a slot with a higher number of lanes (e.g., a x4 board into a x8 slot).
A PCI Express link auto-negotiates between the PCI Express devices to establish communication at the
lowest common interface link between the device and the card slot. The motherboard can reconfigure the
PCIe links for optimum system performance. This allows a x16 PCIe card to operate in a x16 PCIe
mechanical slot even though the slot is driven with a x8 PCI Express electrical link.
For more information, refer to the PCI-SIG’s
PCI Express® Base Specification 2.0
.
2-1
TRENTON
Technology
Inc.
