User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH
Page 4
2.
BRIEF DESCRIPTION
This User's Manual describes the hardware of TQMa8XxS revision 03xx in combination with the MB-SMARC-2 and refers to some
software settings. The MB-SMARC-2 serves as an evaluation board for the TQMa8XxS. A certain TQMa8XxS derivative does not
necessarily provide all features described in this User's Manual. This User's Manual does also not replace the NXP i.MX 8X
Reference Manual (2). The CPU derivatives provide dual, and quad ARM
®
Cortex
®
-A35 cores, and up to two Dual ARM
®
Cortex
®
-
M4 co-processors. In addition, the CPUs include an OpenGL ES 3.0 or 3.1 GPU as well as a VPU supporting up to 4K h.265 decoder.
The TQMa8XxS is a universal Minimodule based on these NXP ARM
®
Cortex
®
-A35 i.MX 8X CPUs, see also Table 3.
An i.MX 8X Cortex
®
-A35 core typically operates at 1.2 GHz.
2.1
Block diagram i.MX 8X
Figure 1:
Block diagram i.MX 8X CPU
(Source:
