TQ Ma8XxS User Manual Download Page 49 | Manualshive

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TQ Ma8XxS User Manual Download Page 49

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH

Page 44

8.2

References

Table 26:

Further applicable documents

No.

Name

Rev., Date

Company

(1)

i.MX8QuadXPlus/8DualXPlus Applications Processor Datasheet

Version 2, 02.06.2016

(2)

Reference Manual of i.MX 8QuadXPlus and 8DualXPlus

Rev. 0, 05/2020

(3)

i.MX 8X Mask Set Errata for Mask 0N99Z

1, 20.05.2020

(4)

PF8100/PF8200 PMIC Datasheet

Rev. 11, 02/2021

(5)

i.MX8 QM/i.MX8 QXP Hardware Developer’s Guide

V1.0, 01/2020

(6)

SMARC Hardware Specification V200

Version 2, June 2, 2016

(7)

MB-SMARC-2 User’s Manual

– current –

(8)

TQMa8XxS Support-Wiki

– current –

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Summary of Contents for Ma8XxS

Page 1: ...TQMa8XxS User s Manual TQMa8XxS UM 0101 25 01 2022...

Page 2: ...s 12 3 2 2 Memory 13 3 2 2 1 LPDDR4 SDRAM 13 3 2 2 2 eMMC NAND flash 13 3 2 2 3 QSPI NOR flash 14 3 2 2 4 EEPROM 15 3 2 2 5 SE97B EEPROM with temperature sensor 15 3 2 3 RTC 16 3 2 3 1 i MX 8X interna...

Page 3: ...Structural requirements 38 5 SOFTWARE 38 6 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS 39 6 1 EMC 39 6 2 ESD 39 6 3 Operational safety and personal security 39 6 4 Climate and operational conditio...

Page 4: ...with discrete RTC 17 Table 11 USB ports 20 Table 12 Assembly option USB3_EN_OC 20 Table 13 I2 C interface 24 Table 14 I2 C addresses 25 Table 15 GPIO pins and alternative functions 25 Table 16 Pin ass...

Page 5: ...diagram Audio 22 Figure 18 Block diagram SPI 23 Figure 19 Block diagram eSPI 23 Figure 20 Block diagram Serial Ports 23 Figure 21 Block diagram CAN 24 Figure 22 Block diagram PCI Express 24 Figure 23...

Page 6: ...d and trademarks are rightly protected by a third party 1 3 Disclaimer TQ Systems GmbH does not guarantee that the information in this User s Manual is up to date correct complete or of good quality N...

Page 7: ...nt details or aspects for working with TQ products Command A font with fixed width is used to denote commands contents file names or menu items 1 7 Handling and ESD tips General handling of your TQ pr...

Page 8: ...rer s specifications of the components used for example CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and reliable op...

Page 9: ...described in this User s Manual This User s Manual does also not replace the NXP i MX 8X Reference Manual 2 The CPU derivatives provide dual and quad ARM Cortex A35 cores and up to two Dual ARM Cortex...

Page 10: ...4 ARM Cortex A35 and 1 ARM Cortex M4F Derivatives i MX 8DualX i MX 8DualXPlus i MX 8QuadXPlus Standard form factor according to SMARC 2 0 82 mm x 50 mm Up to 4 GByte LPDDR4 SDRAM 32 bit Up to 32 Gbyt...

Page 11: ...loader which is preinstalled on the TQMa8XxS and the BSP provided by TQ Systems GmbH see also section 5 i MX 8QXP i MX 8DXP i MX 8DX 1x LPDDR4 SMARC pin strip 314 Pins e MMC 5 1 EEPROM Temperature se...

Page 12: ...teristics are to be taken from the i MX 8X Data Sheet 1 the i MX 8X Reference Manual 2 and the PMIC Data Sheet 6 Some signals are not present on the TQMa8XxS with i MX 8X Dual CPU or they have differe...

Page 13: ...I_N2 P23 S24 GBE1_MDI_N2 GBE1 A A GBE0 GBE0_MDI_P2 P24 S25 GND Power 0 V O 3 3 V GBE0 GBE0_LINK_ACT P25 S26 GBE1_MDI_P3 GBE1 A A GBE0 GBE0_MDI_N1 P26 S27 GBE1_MDI_N3 GBE1 A A GBE0 GBE0_MDI_P1 P27 S28...

Page 14: ...P70 S71 USB2_SS_TX_P USB2_SS 1 0 V O I O 3 3 V USB2 USB2_EN_OC P71 S72 USB2_SS_TX_N USB2_SS 1 0 V O RFU P72 S73 GND Power 0 V RFU P73 S74 USB2_SS_RX_P USB2_SS 1 0 V I I O 3 3 V USB3 USB3_EN_OC P74 S7...

Page 15: ...O AK18 AH28 I 1 8 V CONFIG IMX_ONOFF P128 S129 MIPI_DSI0_DN1 LVDS DSI 1 8 V O AJ17 AA29 O 1 8 V SER UART0_TX P129 S130 GND Power 0 V AB32 I 1 8 V SER UART0_RX P130 S131 MIPI_DSI0_DP2 LVDS DSI 1 8 V O...

Page 16: ...atives is assembled Table 3 i MX 8X derivatives TQMa8XxS variant CPU derivative Cortex A35 clock Cortex M4 clock TJ temperature range TQMa8XDS xx i MX 8DualX 1 2 GHz 264 MHz 40 C to 125 C TQMa8XDPS xx...

Page 17: ...nterfaces and its configuration is to be taken from the i MX 8X Data Sheet 1 and the i MX 8X Reference Manual 2 Alternatively an image can be loaded into the internal RAM via serial downloader i MX 8X...

Page 18: ...s of the cells the power consumption is thereby reduced or the memory is used energy neutral compared to use without ECC at higher temperatures The IO voltage of the LPDDR4 is 1 1 V The standard memor...

Page 19: ...SPIA_DATA 3 0 SPI NOR Octal Twin Quad QSPI NOR D 3 0 D 7 4 SMARC Pins QSPIA_DQS DQS QSPIA_SS 1 0 _B C1 QSPIA_SCLK QSPIB_DATA 3 0 QSPIB_SS 1 0 _B QSPIB_SCLK S1 S2 C2 ESPI_CK ESPI_IO_ 4 0 ESPI_CS 1 0 ES...

Page 20: ...ected PWP or Reversible Write Protected RWP by software The upper 128 bytes address 80h to FFh are not write protected and can be used for general purpose data storage The EEPROM also provides a tempe...

Page 21: ...oefficient max 0 04 x 10 6 C2 The RTC power domain SNVS of the CPU is supplied by the PMIC through the internal controller VSNVS This is supplied either from the module input voltage V_VDD_IN or from...

Page 22: ...A LDO3OUT I2C VDD VDD_IN 3 5 25 V VIN i MX 8X I2C0 Figure 9 Block diagram RTC supply TQMa8XxS with discrete RTC Note SNVS domain supply The SNVS domain is not buffered by LICELL for TQMa8XxS variants...

Page 23: ...i MX 8X have one trigger signal PPS each but this signal is only multiplexable at the CPU ball F28 For the SDP signal a bidirectional level converter from 1 8 V to 3 3 V is required The SN74LVC1T45 f...

Page 24: ...USB0 USB 2 0 OTG USB SS3 0R Figure 12 Block diagram USB interfaces At port USB0 the USB OTG1 port of the CPU is connected because the SMARC standard defines the force recovery function at this port Th...

Page 25: ...ion signals The hub has separate pins for these functions To bring them together two small CPLDs with specific programming are provided on the module The pull up resistors to be placed on the module a...

Page 26: ...2C L 1 0 AUX HPD LVDS0 DSI0_D 3 0 DP0_AUX 0R DP0_LANE 1 0 DP0_HPD MIPI_DSI0_CLK MIPI_DSI1_DATA 3 0 MIPI_DSI1_CLK LVDS0 DSI0_CLK LCD 1 0 _BLKT_EN LCD 1 0 _VDD_EN LCD 1 0 _BLKT_PWM LVDS1 DSI1_D 3 0 LVDS...

Page 27: ...e able to boot from SD card a high level must be applied to the signal at boot time However SDIO_PWR_EN is low by default i MX 8X SMARC Pins USDHC1_CD SDIO_CMD SDIO_D 3 0 SDIO_CD USDHC1_DATA 3 0 SDIO_...

Page 28: ...d if other devices than QSPI memory are connected The signals ESPI_RESET and ESPI_ALERT0 are realized with GPIOs of the CPU ESPI_ALERT1 is not used i MX 8X SMARC pins GPIO ESPI_CS 1 0 ESPI_IO_ 3 0 ESP...

Page 29: ...e module since SMARC defines the pins for the clock as outputs and a commissioning with the CPU internal reference clock has not succeeded so far The 9FGV0241AKILF from IDT is used for this purpose wh...

Page 30: ...e of the i MX 8X is connected to 1 8 V by default The reference voltage can also be applied externally through the GPIO0 pin using the placement option Additional interfaces are available at the GPIO...

Page 31: ...Table 16 Pin assignment JTAG connector Pin Name SMARC spec I O Signal CPU ball 1 VDD_JTAG_IO P V_1V8 2 JTAG_TRST NC 3 JTAG_TMS I JTAG_TMS AG35 4 JTAG_TDO O JTAG_TDO AF32 5 JTAG_TDI I JTAG_TDI AH34 6...

Page 32: ...he high edge at CARRIER_PWR_ON The PMIC pin STANDBY must be configured as high active since the CPU actively drives the signal low i MX 8X SMARC Pins CARRIER_STBY SCU_PMIC_STANDBY PMIC_STBY_REQ PMIC S...

Page 33: ...ings the complete parallel CSI interface is led out The signals do not conform to the SMARC specification and are therefore connected by optional 0 bridges The 0 bridges are not equipped as standard N...

Page 34: ...output signals BOOT_MODE 3 0 are connected to programmable IO pins of the CPLD Since due to the PMIC sequencing the CPU reset signal is strongly delayed 100 ms it is ensured that valid output signals...

Page 35: ...of the TQMa8XxS PF8100 SMARC Pins i MX 8X SW1 2 VDD_GPU LDO1 VIN VDD_IN VDD_RTC LICELL 3 0 V VDD_DDR_VDDQ VDD_XXX_1P8 VDD_USB_3P3 VDD_ANA 1 0 _1P8 VDD_A35 1 1 V 1 1 V 1 8 V 1 8 V 3 3 V 1 0 V 3 0 V SW3...

Page 36: ...an be found in the application note AN12338 from NXP The following table shows the power consumption values of the TQMa8XxS at supply voltages of 3 3 V and 5 0 V Table 19 TQMa8XxS power consumption wi...

Page 37: ...a 3 3 V level 3 8 2 Voltage monitoring The 3 3 V input voltage is monitored on the TQMa8XxS If the input voltage is too low a reset is triggered until the input voltage is within the defined range ag...

Page 38: ...t power up the following sequence must be met on the carrier board The supply voltage of 3 3 V for the TQMa8XxS is present and the carrier board supply of 3 3 V is activated with TQMa8XxS voltage V_1V...

Page 39: ...WR_BAD I VDD_IN status module voltage supply from Carrier enable signal for PMIC high active buck boost and linear regulator is activated by default when V_3V3_IN is switched on to activate float or c...

Page 40: ...s The following table shows some suitable mating connectors for the carrier board Table 21 TQMa8XxS mating connectors Manufacturer Part Connector height Board To Board JAE MM70 Series 4 3 mm 6 7 mm 1...

Page 41: ...20 0 12 mm Printed circuit board thickness C 2 27 0 15 mm Processor height typically highest component D 0 43 0 09 mm Installation space under the module E 5 02 0 20 mm Total height from top edge of...

Page 42: ...ends on connector on carrier board The TQMa8XxS weighs approximately 17 g 4 5 Protection against external effects As an embedded module the TQMa8XxS is not protected against dust external impact and c...

Page 43: ...t component Inadequate cooling connections can lead to overheating of the TQMa8XxS and thus malfunction deterioration or destruction 4 7 Structural requirements The TQMa8XxS has a low retention force...

Page 44: ...directly Direct signal routing without stubs for multi pole interfaces e g LC display As part of the development an EMC test was performed with the starter kit MB SMARC 2 REV 02xx in accordance with E...

Page 45: ...Relative humidity operating storage 10 to 90 Not condensing Attention Destruction or malfunction TQMa8XxS heat dissipation The TQMa8XxS belongs to a performance category in which a cooling system is...

Page 46: ...tery No batteries are assembled on the TQMa8XxS 7 6 Packaging The TQMa8XxS is delivered in reusable packaging 7 7 Other entries By environmentally friendly processes production equipment and products...

Page 47: ...nly Memory EMC Electromagnetic Compatibility eMMC embedded Multimedia Card ESD Electrostatic Discharge eSPI enhanced Serial Peripheral Interface EU European Union EuP Energy using Products FR 4 Flame...

Page 48: ...ccess Memory REACH Registration Evaluation Authorisation and restriction of Chemicals RF Radio Frequency RFU Reserved for Future Usage RGB Red Green Blue RGMII Reduced Gigabit Media Independent Interf...

Page 49: ...02 06 2016 NXP 2 Reference Manual of i MX 8QuadXPlus and 8DualXPlus Rev 0 05 2020 NXP 3 i MX 8X Mask Set Errata for Mask 0N99Z 1 20 05 2020 NXP 4 PF8100 PF8200 PMIC Datasheet Rev 11 02 2021 NXP 5 i M...

Page 50: ...TQ Systems GmbH M hlstra e 2 l Gut Delling l 82229 Seefeld Info TQ Group TQ Group...

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