TQ Ma8XxS, User Manual

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User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 24
3.3.10 CAN bus
Both CAN interfaces are provided at the SMARC pins. CAN0 of the SMARC pins is connected to the UART2 balls of the CPU. The
CAN1 pins use FLEXCAN2 of the CPU.
i.MX 8X SMARC-Pins
CAN1_RX/TX
CAN0_RX/TX UART2_RX/TX
FLEXCAN2_RX/TX
Figure 21: Block diagram CAN
3.3.11 PCI Express
A total of four PCIe interfaces are provided in the SMARC standard, of which only PCIE_A is provided by the i.MX 8X. PCIE_[D:B]
are not provided. PCIE_WAKE# has a pull-up to 3.3 V on the module.
Furthermore, a clock driver is equipped on the module, since SMARC defines the pins for the clock as outputs and a
commissioning with the CPU-internal reference clock has not succeeded so far. The 9FGV0241AKILF from IDT is used for this
purpose, which can be configured via I2C0.
i.MX 8X SMARC-Pins
PCIE_A_REFCK
PCIE_A_TX PCIE0_TX0
PCIE_A_RX PCIE0_RX0
PCIE_REFCLK100M
PCIE_A_RST#
PCIE_WAKE# PCIE_CTRL0_PERST#
PCIE_CTRL0_WAKE#
220nF
9FGV0241
DIF0 DIF1
Figure 22: Block diagram PCI Express
3.3.12 I 2 C
The I
2
C interfaces of the CPU are provided at the SMARC connector as follows:
Table 13: I 2 C interface
SMARC pins i.MX 8X interface Pull-up resistors
I2C_GP I2C0 2,49 kΩ
I2C_PM PMIC_I2C 1,5 kΩ
I2C_LCD MIPI_DSI0_I2C0
2,49 kΩ
I2C_CAM1 MIPI_CSI0_I2C0 2,49 kΩ
Standard-compliant pull-up resistors are provided on all I
2 C signals on the TQMa8XxS.