User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH
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Signal
I/O
Level
Description
Usage
CHARGING#
I
1.8 V
Status Charging
i.MX 8X GPIO0_IO14
CHARGER_PRSNT#
I
1.8 V
Status Charging voltage
i.MX 8X GPIO0_IO15
TEST#
I
1.8 V
Test functions
NC; 10k Pull-up to V_1V8
SMB_ALERT_1V8#
I
1.8 V
SMBus interrupt
i.MX 8X GPIO0_IO19
(Alt: MCLK_IN0)
In order for the signal CARRIER_STBY# to correspond to the default from SMARC Power Sequencing, it is logically AND-linked to
the signal CARRIER_PWR_ON. In sequencing, the high edge at CARRIER_STBY# must not occur before the high edge at
CARRIER_PWR_ON. The PMIC pin STANDBY must be configured as high-active since the CPU actively drives the signal low.
i.MX 8X
SMARC-Pins
CARRIER_STBY#
SCU_PMIC_STANDBY
PMIC_STBY_REQ
PMIC
STANDBY
PGOOD
&
CARRIER_PWR_ON
CARRIER_PWR_ON
Figure 24: Block diagram CARRIER_STBY#
Another part of the signals is used to control the PMIC.
3.5
Trust Secure Element
Depending on the module variant, a Trust Secure Element (TSE) is available on the TQMa8XxS. This is connected to the I2C0 bus
of the i.MX 8X via a level translator.
SMARC-Pins
SE050
i.MX 8X
DP1_HPD
DP1_LANE2-
DP1_AUX-
I2C1
I2C_SDA
IO1 / SDA
IO2 / SCL
RST_N
CLK
LB
LA
DP
DP1_AUX_SEL
MIPI_CSI0_GPIO0_00
MIPI_CSI0_GPIO0_01
I2C_SCL
Level-
Translator
Figure 25:
Block diagram Trust Secure Element
