User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH
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i.MX 8X
ENET0
RGMII0
ENET1
RGMII1
PHY #1
DP83867
PHY #2
DP83867
SMI
SMARC pins
GBE0
GBE1
Figure 11:
Block diagram Ethernet PHYs
3.3.2
USB
The SMARC standard defines a total of six USB ports, which are wired as shown in the following table. USB2 and USB3 can be
used for USB 3.0, so they have the additional differential superspeed signals (TX/RX).
Both OTG ports of the i.MX 8X can be used for the serial downloader.
Furthermore, due to the USB architecture in the i.MX 8X, USB OTG2 is used together with USB SS3 for USB 3.0 functionality.
i.MX 8X
SMARC-Pins
USB OTG2
USB2
TUSB8041
USB 3.0 Host
USB5
USB1
USB3
USB4
NC
USB 2.0 Host
USB 3.0 Host
USB 2.0 Host
USB OTG1
USB0
USB 2.0 OTG
USB SS3
0R
Figure 12: Block diagram USB interfaces
At port USB0 the USB OTG1 port of the CPU is connected, because the SMARC standard defines the force recovery function at
this port. The second USB OTG port (OTG2) of the i.MX 8X is used for the USB hub. Since the USB hub is a placement option,
OTG2 can be applied directly to USB3 of the SMARC pins via 0R bridges. USB3 was chosen because the signals OTG2_VBUS and
OTG2_ID are also available there.
The connection of the control signals of USB0 and USB3 is shown in figure below. The signal USB0_EN_OC# is realized by means
of an open-drain buffer and connected to the corresponding pins of the USB-OTG1 port of the i.MX 8X.
i.MX 8X
SMARC-Pins
USB3_VBUS_DET
USB_OTG1_VBUS
USB0_EN_OC#
USB_OTG1_ID
USB_OTG1_PWR
USB_OTG1_OC
USB_OTG2_VBUS
USB_OTG2_ID
USB0_OTG_ID
USB0_VBUS_DET
USB3_OTG_ID
3,3V
5V
NP
V_3V3
V_3V3
Figure 13:
Connection of control signals USB0 and USB3
