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TXZ Family

Serial Peripheral Interface

2019-02-28

45 / 67

Rev. 3.0

3.3.9.1. Transmit Completion Interrupt/Receive Completion Interrupt

(1)

Master operation

Each single transfer, burst transfer and continuously transfer, transmit completion interrupt occurs (Note) when
TSPIxCS0/1/2/3 is deasserted in transmission or full duplex communications.

Each single transfer, burst transfer and continuously transfer, receive completion interrupt occurs (Note) when
TSPIxCS0/1/2/3 is deasserted in reception or full duplex communications.

Note: When use SIO mode, it cannot confirm the TSPIxCS0/1/2/3 deassertion. The timing of interrupt occurrence is

depends on value of

[TSPIxFRMR0]

<SCKCSDL>.

(2)

Slave operation

A transmit completion interrupt occurs in transmission or full-duplex communication. A transmit completion
interrupt occurs at the timing of one frame transfer completion in single transfer or continuous transfer, or at the
end of the last frame transfer in burst transfer. A reception completion interrupt occurs in receive or full-duplex
communication. The receive completion interrupt occurs at the timing of one frame transfer completion in the case
of single transfer or continuous transfer, or at the end of the last frame transfer in the case of burst transfer.

3.3.9.2. Transmit FIFO Interrupt/Receive FIFO Interrupt

A transmit FIFO interrupt occurs when the following conditions are met.

•

[TSPIxSR]

<TLVL[3:0]> is greater one than the transmit FIFO interrupt condition (fill level) specified in

[TSPIxCR2]

<TIL[3:0]>.

•

Data is transferred from the transmit FIFO to the transmit shift register. fill level of the transmit FIFO is
decreased by one, and the level is changed to the same value of transmit interrupt generation condition (fill
level).

A transmit FIFO interrupt occurs when the following conditions are met.

•

[TSPIxSR]

<RLVL[3:0]> is less one than receive interrupt generation condition (fill level) specified in

[TSPIxCR2]

<RIL[3:0]>.

•

Data is transferred from the receive shift register to the receive FIFO. fill level of the receive FIFO is
increased by one, and the level is changed to the same value of receive interrupt generation condition (fill
level).

3.3.9.3. Error Interruption

The following error interrupt is generated. In case, please process appropriately.

(1) Parity Error Interrupt

When a parity error is detected, a parity error interrupt is generated.

If a parity is enabled, a parity is calculated using received data that is received one bit previous to the last
data of the frame.

The calculated parity is compared with the received parity that is the last bit of frame. If they do not match,
a parity error interrupt occurs.

An interrupt generates when receive frame data is stored to the receive FIFO.

(2) Overrun error interrupt and underrun error interrupt

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Summary of Contents for TXZ SERIES

Page 1: ...ial Peripheral Interface 2019 02 28 1 67 Rev 3 0 2017 2019 Toshiba Electronic Devices Storage Corporation 2019 02 32 bit RISC Microcontroller TXZ Family Reference Manual Serial Peripheral Inteface TSPI B Revision 3 0 ...

Page 2: ... 29 3 3 2 3 Master Slave selection 29 3 3 3 Buffer Structure 29 3 3 3 1 Data Length and FIFO Operation 30 3 3 4 Communication Operation mode 32 3 3 4 1 Full duplex communication mode 32 3 3 4 2 Transmit mode 34 3 3 4 3 Receive mode 35 3 3 5 Transfer mode 36 3 3 5 1 Single transfer 36 3 3 5 2 Burst transfer 36 3 3 5 3 Continuously transfer 36 3 3 6 Data sampling timing 37 3 3 7 Special control 40 3...

Page 3: ... TSPIxCR0 TSPI Control Register 0 49 4 2 2 TSPIxCR1 TSPI Control Register 1 50 4 2 3 TSPIxCR2 TSPI Control Register 2 52 4 2 4 TSPIxCR3 TSPI Control Register 3 54 4 2 5 TSPIxBR TSPI Baud Rate Register 54 4 2 6 TSPIxFMTR0 TSPI Format Control Register 0 55 4 2 7 TSPIxFMTR1 TSPI Format Control Register 1 57 4 2 8 TSPIxDR TSPI Data Register 57 4 2 9 TSPIxSR TSPI Status Register 58 4 2 10 TSPIxERR TSPI...

Page 4: ...IO mode master 39 Figure 3 19 Data sampling timing of SIO mode slave 39 Figure 3 20 Transfer format and timing adjustment Example for 2nd edge sampling 40 Figure 3 21 Idle state in SPI mode and the transmit pin status 42 Figure 3 22 Idle state in SIO mode and the transmit pin status 42 Figure 3 23 Circuit of interrupt request 44 Figure 3 24 Overrun error and underrun error 46 List of Tables Table ...

Page 5: ...TXZ Family Serial Peripheral Interface 2019 02 28 5 67 Rev 3 0 Preface Related document Document name Clock Control and Operation Mode Exception Input Output Ports Product Information ...

Page 6: ...32A0RUNA T32A1RUNA T32A2RUNA T32AxRUNA The bit range of a register is written like as m n Example Bit 3 0 expresses the range of bit 3 to 0 The configuration value of a register is expressed by either the hexadecimal number or the binary number Example ABCD EFG 0x01 hexadecimal XYZn VW 1 binary Word and Byte represent the following bit length Byte 8 bits Half word 16 bits Word 32 bits Double word ...

Page 7: ...torage Technology Inc Super Flash is registered trademark of Silicon Storage Technology Inc All other company names product names and service names mentioned herein may be trademarks of their respective companies Arm Cortex and Thumb are registered trademarks of Arm Limited or its subsidiaries in the US and or elsewhere All rights reserved ...

Page 8: ...erms and Abbreviation Some of abbreviations used in this document are as follows ACK Acknowledgement DMA Direct Memory Access FIFO First In First Out LSB Least Significant Bit MSB Most Significant Bit SIO Serial Input Output TSPI Toshiba Serial Peripheral Interface ...

Page 9: ... Serial Peripheral Interface has four operation mode as SPI SIO mode and the clock master clock slave mode One channel unit which is built in TSPIxTXD TSPIxRXD TSPIxSCK TSPIxCS0 TSPIxCS1 TSPIxCS2 TSPIxCS3 and TSPIxCSIN can be transmit and receive circuit functions are as below ...

Page 10: ... logic is possible Ganged Control Interruption Transmit interrupt Transmit completion interrupt Transmit FIFO interrupt Receive interrupt Receive completion interrupt Receive FIFO interrupt Error Interrupt Vertical parity error interrupt Trigger error interrupt Various status detection TSPI modify status Transmit shift operation Transmit completion Transmit FIFO fill level empty detection Receive ...

Page 11: ...er 2 to 255 times transfer Continuously transfer No limit of transfer times specification Data sampling timing Data is sampled with 2nd edge CS control TSPIxCSIN Polarity Selection of positive logic negative logic is possible Ganged Control Interruption Transmit interrupt Transmit completion interrupt Transmit FIFO interrupt Receive interrupt Receive completion interrupt Receive FIFO interrupt Err...

Page 12: ...tinuously transfer No limit of transfer times specification Data sampling timing Data is sampled with 2nd edge Ganged Control Interruption Transmit interrupt Transmit completion interrupt Transmit FIFO interrupt Receive interrupt Receive completion interrupt Receive FIFO interrupt Error Interrupt Vertical parity error interrupt Trigger error interrupt Various status detection TSPI modify status Tr...

Page 13: ...mes specification Data sampling timing Data is sampled with 2nd edge Ganged Control Interruption Transmit interrupt Transmit completion interrupt Transmit FIFO interrupt Receive interrupt Receive completion interrupt Receive FIFO interrupt Error Interrupt Vertical parity error interrupt Over run interrupt Under run interrupt Various status detection TSPI modify status Transmit shift operation Tran...

Page 14: ...ister TSPIxSR DMA Control Interrupt Control Transmit DMA request TSPIxTX_DMA Receive DMA request TSPIxRX_DMA Error Interrupt request INTTxERR Transmit Control Transmit Data Length Control Counter Transmit FIFO Transmit Shift Register Receive Control Receive Counter Receive data Length Control Register Receive FIFO Receive Shift Register TSPIxRXD TSPIxCS1 TSPIxCS2 TSPIxCS3 TSPIxCS0 TSPIxCSIN 1 2 Tr...

Page 15: ...for slave operation Input Input Output Ports 9 TSPIxTXD Serial data of transmission Output Input Output Ports 10 TSPIxRXD Serial data of reception Input Input Output Ports 11 INTTxTX Transmit interrupt request Output Exception 12 INTTxRX Receive interrupt request Output Exception 13 INTTxERR Error interrupt request Output Exception 14 TSPIxTRG Trigger input for start communication Input Product In...

Page 16: ...control set as 1 Please perform needed setup such as communicate mode transfer mode and a transfer format after checking that TSPIxSR TSPISUE TSPI modify status flag is 0 3 1 3 Start and stop transfer There are two methods for a transfer start in the case of full duplex communication mode and transmitting mode 1 Write Data to data register TSPIxDR after wrote 1 to TSPIxCR1 TRXE for enable communic...

Page 17: ... transfer direction MSB LSB first and frame length set up TSPIxFMTR0 TSPI format control register 0 When specifying the enable parity and even odd parity set up TSPIxFMTR1 TSPI format control register 1 Note When the parity function is enabled data length is 31 bits at maximum Figure 3 1 Data format ...

Page 18: ...y 32 bit frame length Figure 3 2 shows a transmit receive operation without parity MSB first 32 bit data length In the transmission data in the transmit FIFO is copied to D31 through D0 in the shift register Transmit data copied to shift register is transferred sequentially from D31 through D0 on serial clock In the reception receive data is stored in the D0 of the shift register Shift operation r...

Page 19: ...e transmit FIFO is copied to D15 through D0 in the shift register Transmit data copied to shift register is transferred sequentially from D15 through D0 on serial clock In the reception receive data is stored in the D0 of the shift register Shift operation repeats on serial clock If the shift register stores 16 bit reception data data is copied to the receive FIFO Figure 3 3 MSB first 16 bit data ...

Page 20: ...ed bit by bit when the data is copied to the shift register Transmit data copied to the shift register is transferred from D0 until reaching 32 bit shifted data on serial clock In the reception receive data is stored in D31 of the shift register Shift operation repeats on serial clock If the shift register stores 32 bit reception data data is sorted bit by bit and copied to the receive FIFO Figure...

Page 21: ...orted bit by bit when the data is copied to the shift register Transmit data copied to shift register is transferred from D15 until reaching 16 bit shifted data on serial clock In the reception receive data is stored in the D15 of the shift register Shift operation repeats on serial clock If the shift register stores 16 bit reception data data is sorted bit by bit and copied to the receive FIFO Fi...

Page 22: ...ansmit receive operation with a parity bit MSB first 31 bit data length A frame length is 32 bit data length including a parity bit In the transmission data D30 through D0 in the transmit FIFO are copied to D31 through D1 in the shift register At the same time a parity is calculated using data D31 through D1 in the shift register The result is stored in the D0 in the shift register Subsequently tr...

Page 23: ...1 in the shift register At the same time a parity is calculated using data D14 through D0 The result is stored in D0 in the shift register Subsequently transmit data in the shift register and parity data are sequentially transferred from D15 through D0 in the shift register on serial clock In the reception receive data is stored in D0 of the shift register Shift operation repeats on serial clock I...

Page 24: ...gister At the same time a parity is calculated using data D30 through D0 The result is stored in the D0 in the shift register Consequently transmit data in the shift register and a parity data are sequentially transferred from D31 to D0 in the shift register on serial clock In the reception receive data is stored in the D0 of the shift register Shift operation repeats on serial clock If the shift ...

Page 25: ...rom D31 in the shift register At the same time a parity is calculated using data D14 through D0 The result is stored in the D16 in the shift register Subsequently transmit data in the shift register and parity data are sequentially transferred from D31 through D16 in the shift register on serial clock In the reception receive data is stored in the D0 of the shift register Shift operation repeats o...

Page 26: ... 1 256 1 512 Figure 3 10 Transfer clock generation circuit The prescaler dividing ΦT0 from 1 1 to 1 512 ΦT0 to ΦT256 Divided clock can be selected by TSPIxBR BRCK The example of calculation of transfer clock frequency transfer clock is shown below transfer clock ΦT0 TSPIxBR BRCK 1 x TSPIxBR BRS 1 N 1 2 x 1 2 4 8 16 to 256 512 N 1 2 3 4 to 16 At this time please keep below condition The case of TSP...

Page 27: ...k TSPIxSCK 2 transfer clock ΦTx 2 product transfer clock 20MHz fclk MHz ΦT0 MHz ΦTx MHz transfer clock TSPIxSCK MHz Usability 40 40 40 20 40 20 20 20 40 20 20 10 40 10 10 10 20 20 10 10 20 10 10 5 Can be used Cannot be used Note1 Regarding to maximum operation frequency and maximum transfer clock please refer to Electric Characteristics of datasheet Note2 fclk is either the system clock fsys or hi...

Page 28: ...n addition maximum four chip select signal Output TSPIxCS0 1 2 3 are built in and it can communicate with four external slave devices Moreover one chip select signal input TSPIxCSIN is built in and it can communicate with one master device Note The number of chip select outputs TSPIxCS0 1 2 3 are different product by product Please refer to the datasheet and reference manual Product Information Ma...

Page 29: ...as Master the device outputs transfer clock or Slave transfer clock is input to the device When 0 is set to TSPIxCR1 MSTR the TSPI operates as Slave When 1 is set to TSPIxCR1 MSTR the TSPI operates as Master 3 3 3 Buffer Structure The transmit buffer and receive buffer are independent respectively Each buffer has a double buffering structure consisting of the FIFO and 32 bit width shift register T...

Page 30: ...ata to TSPIxRXD is captured by the shift register When a certain frame length is transferred if the FIFO has space received data in the shift register is copied to the FIFO Data is stacked in the FIFO in the order starting from f0 f1 f2 f3 f4 f5 f6 and f7 If the DMAC or CPU reads data register the contents of the stage in the receive FIFO directed by the receive FIFO pointer are read On the first ...

Page 31: ... starting from f1 L f1 H f2 L f2 H f3 L and f3 H If the DMAC or CPU reads data register contents of the stage in receive FIFO directed by receive FIFO pointer is read On the first read operation the first stage f0 L of the FIFO is copied to the lower 16 bits in the data register The contents in the second stage f0 H of the FIFO is copied to the upper 16 bits in data register The receive FIFO point...

Page 32: ...ansmit FIFO TSPIxSR TLVL becomes 1 e Buffered data in the transmit FIFO is copied to the shift register so that TSPIxSR TLVL becomes 0 After a serial clock delay time ta specified by TSPIxFMTR0 CSSCKDL has elapsed TSPIxSCK starts outputting serial clock f Since TSPIxSR TLVL changes to 0 from 1 a transmit FIFO interrupt or transmit DMA request occurs g On the last rising edge of serial clock all bi...

Page 33: ... TSPIxSR RLVL changes to 1 from 0 a receive FIFO interrupt or receive DMA request occurs j Until the minimum idle time td specified by TSPIxFMTR0 CSINT has elapsed after TSPIxCS0 is deasserted serial transfer does not start and TSPIxCS0 remains deasserted After the minimum idle time td has elapsed TSPIxCS0 is asserted and serial transfer starts ...

Page 34: ...is buffered to the transmit FIFO TSPIxSR TLVL becomes 1 e Since buffered data in the transmit FIFO is copied to the shift register TSPIxSR TLVL becomes 0 After a serial clock delay time ta specified by TSPIxFMTR0 CSSCKDL has elapsed TSPIxSCK starts outputting serial clock f Since TSPIxSR TLVL changed to 0 from 1 a transmit FIFO interrupt or transmit DMA request occurs g Until the minimum idle time...

Page 35: ...ata are captured in the receive shift register and the data is copied to the receive FIFO d Since one stage data is buffered to the receive FIFO TSPIxSR RLVL becomes 1 e Since TSPIxSR RLVL changed to 1 from 0 a receive FIFO interrupt or receive DMA request occurs f After a CS deasserted delay time tb specified by TSPIxFMTR0 SCKCSDL has elapsed after the last rising edge of serial clock TSPIxCS0 is...

Page 36: ...gle transfer In the case of the master in SPI mode TSPIxCS0 1 2 3 is asserted during transfer of one frame and TSPIxCS0 1 2 3 is deasserted when the transfer is completed 3 3 5 2 Burst transfer Burst transfer is the transfer mode that can consecutively transfer multiple frames In SPI mode TSPIxCS0 1 2 3 keeps asserted condition while specified frames are transferring TSPIxCS0 1 2 3 is deasserted w...

Page 37: ... data sampling timing And Table 3 4 is shown Data capture timing Table 3 3 Usability of communication mode and data sampling timing Data Sampling Timing SPI mode SIO mode Master Operation Slave Operation Master Operation Slave Operation 2nd edge 1st edge Can be used Cannot be used Table 3 4 Data capture timing Polarity of idle period of TSPIxSCK TSPIxFMTR0 CKPOL Data capture timing TSPIxFMTR0 CKPH...

Page 38: ...TSPIxCSn Input sampling Output timing SPI mode master 1st edge data sampling CKPHA 0 Internal Clock Input sampling Output timing Internal Clock TSPIxTXD TSPIxRXD CKPOL 0 CKPOL 1 TSPIxSCK CSnPOL 0 CSnPOL 1 TSPIxCSn Internal Clock Input sampling Output timing Internal Clock SPI mode master 1st edge data sampling CKPHA 0 Idle period output is Hi Z TIDLE 00 Hi Z Hi Z Figure 3 16 Data sampling timing o...

Page 39: ...put timing Figure 3 17 Data sampling timing of SPI mode slave SIO mode master 2nd edge data sampling CKPHA 1 TSPIxTXD TSPIxRXD CKPOL 0 CKPOL 1 TSPIxSCK Input sampling Output timing Figure 3 18 Data sampling timing of SIO mode master SIO mode slave 2nd edge data sampling CKPHA 1 TSPIxTXD TSPIxRXD CKPOL 0 CKPOL 1 TSPIxSCK Input sampling Output timing Figure 3 19 Data sampling timing of SIO mode slav...

Page 40: ...ock TSPIxSCK changes To set a serial clock delay time set TSPIxFMTR0 CSSCKDL 2 TSPIxCS0 1 2 3 deassert delay tb is a delay time from the time when TSPIxCS0 1 2 3 is deasserted after serial transfer completion To set a TSPIxCS0 1 2 3 deassert delay time set TSPIxFMTR0 SCKCSDL 3 Interval time between frames in the burst transfer tc is an interval time between frames in the burst transfer To set an i...

Page 41: ...0 10 or Fix to High TIDLE 1 0 11 is once selected And re select to Last data in previous transmission TIDLE 1 0 01 immediately after Then TSPIxTXD is kept previous setting until starts next transmission When a underrun error occurs with a final data output at the time of slave operation the value specified in the TSPIxCR2 TXDEMP is outputted during frame transmission and it changes to the data out...

Page 42: ...10 TSPIxFMTR0 CKHPA 1 Example of outputting low at idle Figure 3 21 Idle state in SPI mode and the transmit pin status TSPIxCR2 TIDLE 1 0 10 TSPIxFMTR0 CKHPA 1 Example of outputting low at idle Figure 3 22 Idle state in SIO mode and the transmit pin status 2nd edge 2nd edge Undefined ...

Page 43: ...the receiving start and the clock will be outputted When FIFO is not full reception is continued And when FIFO is full clock output will be stopped After the number of transferring which set as TSPIxCR1 FC is completed a clock output is stopped and reception is terminated A trigger will be ignored if a trigger is inputted when FIFO is full Moreover error interruption is outputted and a flag TSPIxE...

Page 44: ...INTTXWE Transmit FIFO interrupt TSPIxCR2 INTTXFE Receive interrupt Receive completion interrupt TSPIxCR2 INTRXWE Receive FIFO interrupt TSPIxCR2 INTRXFE Error interrupt Vertical parity error interrupt TSPIxCR2 INTERR Overrun error interrupt Underrun error interrupt Trigger error interrupt INTTxTX INTTxRX INTTxERR Transmit completion interrupt TSPIxCR2 INTTXWE Transmit FIFO interrupt TSPIxCR2 INTTX...

Page 45: ...it FIFO Interrupt Receive FIFO Interrupt A transmit FIFO interrupt occurs when the following conditions are met TSPIxSR TLVL 3 0 is greater one than the transmit FIFO interrupt condition fill level specified in TSPIxCR2 TIL 3 0 Data is transferred from the transmit FIFO to the transmit shift register fill level of the transmit FIFO is decreased by one and the level is changed to the same value of ...

Page 46: ...errun occurs is not received Thus the contents of the receive FIFO and receive shift register are not updated Figure 3 24 Overrun error and underrun error Note1 It depends on TSPIxCR2 TIDLE 1 0 of settings Note2 It depends on TSPIxCR2 TXDEMP of settings 3 Trigger error interrupt In the master operation it is set when communication by a trigger input is not able to be started in the trigger communi...

Page 47: ...t transmit DMA request occurs again 3 3 10 2 Receive DMA request The single DMA request of receive and a burst DMA request of receive will be enabled when TSPIxCR2 DMARE is set to 1 When FIFO has one or more data a single request occurs A burst receive DMA request occurs when a value of TSPIxSR RLVL 3 0 indicating current value of fill level is equal or greater than receive interrupt generation co...

Page 48: ...0x40097000 0x400CC400 0x4006C400 ch10 0x400CC800 0x4006C800 ch11 0x400CCC00 0x4006CC00 Note The channel unit and base address type are different by products Please refer to Product Information of the reference manual for the details Register name x Channel number Address Base TSPI Control Register 0 TSPIxCR0 0x0000 TSPI Control Register 1 TSPIxCR1 0x0004 TSPI Control Register 2 TSPIxCR2 0x0008 TSP...

Page 49: ... communications TSPIE is not initialized by software reset Note Completion of software reset takes two clocks after an instruction is executed When TSPI setting is stopped TSPIE 0 software reset is not applied To perform a software reset consecutively write 10 and then 01 to TSPIxCR0 SWRST 1 0 Software reset register Software reset will become invalid if other TSPI control registers are accessed i...

Page 50: ...I mode 1 SIO mode 12 MSTR 1 R W Master slave selection 0 Slave operation 1 Master operation 11 10 TMMD 1 0 11 R W Transfer mode selection 00 Reserved 01 Transmit only 10 Receive only 11 Full duplex mode Transmit receive If the mode transmit only is selected the process circuit for TSPIxRXD stops If the mode receive only is selected the process circuit for TSPIxTXD stops 9 8 CSSEL 0 R W Selection o...

Page 51: ...orm re set it up after the slave device performs software reset by TSPIxCR0 SWRST Note4 In the slave operation if TRXE is rewritten to 0 communication prohibited when data remains in the transmission buffer FIFO during transmission transmission buffer FIFO should be cleared by TSPIxCR3 TFEMPCLR or should be performed software reset by TSPIxCR0 SWRST then re set it up Note5 When slave operation or ...

Page 52: ...l interrupt of transmit FIFO Fill level setting is by TIL 6 INTTXWE 0 R W Transmit completion interrupt control 0 Disabled 1 Enabled When continuously transfer is completed one frame transfer single transfer is completed and during burst transfer an interrupt is generated at the deassertion timing of TSPIxCS0 1 2 3 when burst transfer is completed 5 INTRXFE 0 R W Receive FIFO interrupt control 0 D...

Page 53: ...bled When DMARE is enabled The DMA request is output when the receive FIFO is less than the level set in RIL It does not depend on the state of TSPIxCR1 TRXE If DMARE is set to 0 while the receive DMA request signal is asserted the request signal is deasserted It is reasserted if it satisfies the receive DMA request signal generation requirement when set again to enable Note1 Depending on the prod...

Page 54: ...e receive FIFO becomes empty and the internal pointer of receive shift register is initialized Since the contents of the transmit FIFO and transmit shift register are not affected on the initialization data remains the previous condition in which transmit buffer is cleared 4 2 5 TSPIxBR TSPI Baud Rate Register Bit Bit Symbol After reset Type Function 31 8 0 R Read as 0 7 4 BRCK 3 0 0000 R W Input ...

Page 55: ... 15 x TSPIxSCK cycles This setup is invalid in continuously transfer and slave operation In SIO mode a interval time between frames equivalent of FINT occurs 19 CS3POL 0 R W Polarity of TSPIxCS3 Master operation 0 Negative logic 1 Positive logic 18 CS2POL 0 R W Polarity of TSPIxCS2 Master operation 0 Negative logic 1 Positive logic 17 CS1POL 0 R W Polarity of TSPIxCS1 Master operation 0 Negative l...

Page 56: ...he time from the assertion of the TSPIxCS0 1 2 3 pin until the TSPIxSCK pin changes in units of the serial clock cycle The setting is valid only in master mode 3 0 SCKCSDL 3 0 0000 R W TSPIxCS0 1 2 3 deassertion delay Last data TSPIxCS0 1 2 3 invalid time 0000 1 x TSPIxSCK 1000 9 x TSPIxSCK 0001 2 x TSPIxSCK 1001 10 x TSPIxSCK 0010 3 x TSPIxSCK 1010 11 x TSPIxSCK 0011 4 x TSPIxSCK 1011 12 x TSPIxS...

Page 57: ...ed 1 Enabled 0 VPM 0 R W Vertical parity mode selection Note2 0 Even parity 1 Odd parity Note1 fclk is either the system clock fsys or high speed clock fc depending on the product For the details refer to Product Information in Reference manual Note2 Do not write VPE and VPM when transfer data remain in the shift register 4 2 8 TSPIxDR TSPI Data Register Bit Bit Symbol After reset Type Function 31...

Page 58: ...er to the receive FIFO 30 24 0 R Read as 0 23 TXRUN 0 R Transmit shift operation flag 0 Stop 1 Operation A status flag indicates the transmit shift operation is ongoing Combination of TXRUN and TFEMP bits indicates the following status TXRUN TFEMP Conditions 0 0 Stop or wait for the next transmission 1 Completed transmission and the transmit FIFO is empty 1 In transmission TXRUN is set when data e...

Page 59: ...ompletion flag 0 1 Receiving is complete A flag that is set at the time when reception is complete This flag is set at the last frame TSPIxCS0 1 2 3 is deasserted in the single transfer burst transfer and continuously transfer after one frame transfer W This bit is cleared by writing 1 0 Don t care 1 Flag is cleared When setting by reception completion and clearing by writing 1 occur simultaneousl...

Page 60: ...o 0 1 Please performs software reset by TSPIxCR0 SWRST During transferring Clear to 0 after finish current frame Clear to 0 after finish current frame After stop transferring Clear to 0 Clear to 0 Table 4 3 Current value of fill level depending on the range of TLVL RLVL Frame length FIFO configuration FIFO stage Range of RLVL when receiving Range of TLVL when transmitting 8 to 16bits 8 stages 0 to...

Page 61: ...n error flag 0 No error 1 Error exists This bit is set when an underrun error occurs W 0 Don t care 1 Flag is cleared This bit is cleared by writing 1 Do not clear the bit during transmission reception 1 OVRERR 0 R Overrun error flag 0 No error 1 Error exists This bit is set when an overrun error occurs W 0 Don t care 1 Flag is cleared This bit is cleared by writing 1 Do not clear the bit during t...

Page 62: ...ceive FIFO or receive shift register is full next frame cannot be transferred At this time TSPIxCS0 1 2 3 stays asserted When reading the receive FIFO data if data in the shift register is automatically transferred to the FIFO the shift register is determined as not full and a transfer is automatically restarted In transmission reception if TRXE is set to stop a transfer is stopped after a frame i...

Page 63: ...rred When reading the receive FIFO data if data in the shift register is automatically transferred to the FIFO the shift register is determined as not full and a transfer is automatically restarted TSPIxCS0 1 2 3 stays asserted until a transfer starts again If a burst transfer is attempted again set 1 to TRXE after TSPIxSR TSPISUE bit was returned to 0 In reception if TRXE is set to stop a transfe...

Page 64: ...e 2019 02 28 64 67 Rev 3 0 Precautions In case of the product which does not have TSPIxCS0 1 2 3 terminals or TSPIxCSIN terminal please use SIO mode that is not using these terminals Do not access the address that is not assigned register ...

Page 65: ... added Figure3 16 added figure3 17 3 18 3 19 3 3 7 1 Polarity of TSPIxCS0 1 2 3 signal and generation timing Added Example for 2nd edge sampling to title of Figure 3 20 3 3 7 3 TSPIxTXD Output during Idle Added Note under Table3 3 Added 2nd edge in Figure 3 21 3 22 Added condition in Figure3 22 Modified Figure 3 22 3 3 8 Communication control by trigger Added description 3 3 9 Interrupt Request Co...

Page 66: ...Note in Table2 1 3 3 1 Transfer clock Tile was modified from Transmission clock to Transfer clock 3 3 1 1 Master operation Modified parameter of 1 x Modified the formula in case of TSPIxCR2 RXDLY 0 Modified fsys to fclk of formula Added Note2 in Table3 1 And modified Note to Note2 3 3 1 2 Slave operation Added the formula of slave operation 3 3 2 1 SPI mode Modified Master device operation to Mast...

Page 67: ...supporting medical equipment equipment used for automobiles trains ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators and devices related to power plant IF YOU USE PRODUCT FOR UNINTENDED USE TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT For details please contact your TOSHIBA sales representative or cont...

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