TXZ Family
Serial Peripheral Interface
2019-02-28
34 / 67
Rev. 3.0
3.3.4.2. Transmit mode
Figure 3.14 shows an operation example of continuously transfer (32-bit frame length, no parity, one-stage of
FIFO) in the transmit mode. (
[TSPIxCR2]
<TIDLE[1:0]>=10)
Figure 3.14 Operation example of transmit mode
a)
Write "1" to
[TSPIxCR1]
<TRXE> to enable the communications
b)
Write data to
[TSPIxDR]
.
c)
If data is written to
[TSPIxDR],
data is written to a stage of FIFO directed by internal transmit FIFO
pointer
.
d)
Since one stage of data is buffered to the transmit FIFO,
[TSPIxSR]
<TLVL> becomes "1".
e)
Since buffered data in the transmit FIFO is copied to the shift register,
[TSPIxSR]
<TLVL> becomes "0".
After a serial clock delay time (t
a
) specified by
[TSPIxFMTR0]
<CSSCKDL> has elapsed, TSPIxSCK
starts outputting serial clock.
f)
Since
[TSPIxSR]
<TLVL> changed to "0" from "1", a transmit FIFO interrupt (or transmit DMA request)
occurs.
g)
Until the minimum idle time (t
d
) specified by
[TSPIxFMTR0]
<CSINT> has elapsed after TSPIxCS0 is
deasserted, serial transfer does not start and TSPIxCS0 remains deasserted. After the minimum idle time
(t
d
) has elapsed, TSPIxCS0 is asserted and serial transfer starts.
a)
b)
c)
e)
[TSPIxDR]
[TSPIxCR]
<TRXE>
[TSPIxSR]
<TLVL[3:0]>
[TSPIxSR]
<RLVL[3:0]>
e)
e)
d)
f)
f)
g)
g)
