TXZ Family
Serial Peripheral Interface
2019-02-28
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Rev. 3.0
3.3.4. Communication Operation mode
3.3.4.1. Full duplex communication mode
Figure 3.13 shows an operation example of full duplex communication in continuously transfer (32-bit frame
length, no parity, one-stage of FIFO). (
[TSPIxCR2]
<TIDLE[1:0]>=10)
Figure 3.13 Operation example of full duplex communication
a)
Write "1" to
[TSPIxCR1]
<TRXE> to enable communications,
b)
Write data to
[TSPIxDR]
.
c)
If data is written to
[TSPIxDR]
, the data is written to the stage of FIFO directed by internal transmit FIFO
pointer.
d)
Since one stage of data is buffered in the transmit FIFO,
[TSPIxSR]
<TLVL> becomes "1".
e)
Buffered data in the transmit FIFO is copied to the shift register, so that
[TSPIxSR]
<TLVL> becomes "0".
After a serial clock delay time (t
a
) specified by
[TSPIxFMTR0]
<CSSCKDL> has elapsed, TSPIxSCK
starts outputting serial clock.
f)
Since
[TSPIxSR]
<TLVL> changes to "0" from "1", a transmit FIFO interrupt (or transmit DMA request)
occurs.
g)
On the last rising edge of serial clock, all bits of receive data are captured by the receive shift register and
copied to the receive FIFO. After a CS deassert delay time (t
b
) specified by
[TSPIxFMTR0]
<SCKCSDL>
has elapsed after the last rising edge of serial clock, TSPIxCS0 is deasserted so that a transmit completion
interrupt and a receive completion interrupt occur.
a)
b)
c)
e)
e)
d)
e)
f)
f)
g)
h)
i)
i)
j)
[TSPIxDR]
[TSPIxCR]
<TRXE>
[TSPIxSR]
<TLVL[3:0]>
[TSPIxSR]
<RLVL[3:0]>
