TXZ Family
Serial Peripheral Interface
2019-02-28
35 / 67
Rev. 3.0
3.3.4.3. Receive mode
Figure 3.15 shows an operation example of continuously transfer (32-bit length, no parity, one stage of FIFO) in
receive mode. (
[TSPIxCR2]
<TIDLE[1:0]>=10)
Figure 3.15
Operation example in receive mode
a)
Write "1" to
[TSPIxCR1]
<TRXE> to enable the communications. Since receive FIFO is not full,
TSPIxCS0 is immediately asserted and serial clock transfer starts.
b)
After a serial clock delay time (t
a
) specified by
[TSPIxFMTR0]
<CSSCKDL> has elapsed, serial clock
starts outputting from TSPIxSCK.
c)
On the last rising edge of serial clock, all bits of receive data are captured in the receive shift register and
the data is copied to the receive FIFO.
d)
Since one stage data is buffered to the receive FIFO,
[TSPIxSR]
<RLVL> becomes "1".
e)
Since
[TSPIxSR]
<RLVL> changed to "1" from "0", a receive FIFO interrupt (or receive DMA request)
occurs.
f)
After a CS deasserted delay time (t
b
) specified by
[TSPIxFMTR0]
<SCKCSDL> has elapsed after the last
rising edge of serial clock, TSPIxCS0 is deasserted and a receive completion interrupt occurs.
g)
Until the minimum idle time (t
d
) specified by
[TSPIxFMTR0]
<CSINT> has elapsed after TSPIxCS0 is
deasserted, serial transfer does not start and TSPIxCS0 remains deasserted. After the minimum idle time
(t
d
) has elapsed, TSPIxCS0 is asserted and serial transfer starts if the receive FIFO is not full.
[TSPIxDR]
[TSPIxCR]
<TRXE>
[TSPIxSR]
<TLVL[3:0]>
[TSPIxSR]
<RLVL[3:0]>
a)
a)
b)
c)
d)
e)
e)
f)
g)
f)
