TXZ Family
Serial Peripheral Interface
2019-02-28
31 / 67
Rev. 3.0
(2) Data length 17 to 32-bit
If 17 to 32-bit data length are used, two stages of the FIFO are used for one frame.
The FIFO has 8 stages, so that it can store four frame data up to four stage levels.
Figure 3.12 Operation in 17 to 32-bit data length
Input data to TSPIxRXD is captured in the shift register.
When a certain frame length is transferred, if the FIFO has a space, received data in shift register is copied
to the FIFO. Data is stacked in the FIFO in the order starting from f0 (L), f0 (H). In the next frame, data is
copied and stacked in the FIFO in the order starting from f1 (L), f1 (H), f2 (L), f2 (H), f3 (L), and f3 (H).
If the DMAC or CPU reads data register, contents of the stage in receive FIFO directed by receive FIFO
pointer is read.
On the first read operation, the first stage f0 (L) of the FIFO is copied to the lower 16 bits in the data
register. The contents in the second stage f0 (H) of the FIFO is copied to the upper 16 bits in data register.
The receive FIFO pointer is incremented by two and directs the third stage of the FIFO.
On the second read operation, f1 is read in the same manner as f0. The receive FIFO pointer directs fifth
stage of the FIFO.
In the subsequent frames, the receive pointer is incremented by two on reading operations, and the contents
fm (L) are copied to the lower 16 bits in the data register; the contents fm (H) are copied to the upper 16 bits
in the data register.
