Toshiba TLP411E, Technical Training Manual

Page: 62 / 84

6-24
Table 6-10 µPD6453GT pin function
Pin No. Name Terminal Name Function
6 V
DD
Power supply terminal Power supply ( 5V) terminal
10 V
SS
GND Connect to system GND.
5 PCL Power on clear terminal
Clear terminal at power on.
Set to L to H when power is turned on.
VRAM lump-release start-up and test mode release operations are
carried out.
4 DATA Serial data input terminal Control data input terminal
2 CLK Clock input terminal
Clock input terminal for data read.
Data which is added to DATA terminal at clock rising period is read.
3 CS Chip select terminal
Serial transmission is acceptable by developing theis terminal from Hi to
Low.
1 BUSY BUSY signal output terminal Serial data input possible/impossible detection terminal
8, 9
OSC
IN
OSC
OUT
LC oscillation I/O terminal I/O terminal for dot clock signal generation oscillator
7 CK
OUT
Clock out terminal Inverted output for OSC
OUT
20 Hsync
Horizontal sync signal input
terminal Dot clock signal oscillator oscillates at signal rising period and sync Hi
level.
19 Vsync
Vertical sync signal input
terminal
Input sync negative.
12, 13, 14
V
R
V
G
V
B
Character signal output
terminal Character signal output terminal corresponding to RGB signals.
Signal output: Positive
15 V
CBL
Composite blanking output
terminal Blanking signal output terminal to cut video signals.
3 output composite signal for color corresponding blanking signal.
16, 17, 18
R
BLK
G
BLK
B
BLK
Character signal
corresponding blanking
output terminal
Blanking signal output terminal to cut video signals.
RBLK, GBLK and BBLK are corresponding to the character signal
outputs VR, VG and VB.
Signal output: Positive
11 V
MON
(MP)
Character signal monitor
output terminal (mask pulse
output terminal) Output positive signal of the composite signals of VR, VG, VB.
(Signal maks pulse is output as positive signal when selecting the mask
pulse function in mask code option.