Toshiba TLP411E, Technical Training Manual

Page: 53 / 84

6-15
Fig. 6-19 PLL Circuit (1) circuit diagram
14
13
12
11
10
9
8
1 2 3 4
8 7 6 5
1
2
3
4
5
6
7
RX77 47
RX78 330
RX79 330
ZX16
TEM2026D
ZX17
TEM2026D
ZX15
TEM2026D
LX21
TEM2103T
V BLK
+5 VD
CX58
0.33 CX61
0.33
CY21
0.01
CY19
16V
0.33
CY23
16V
10
CY22
0.1
RY43
10k
RX80
1k
CX62
16V
10
RX82
3.3k
RY44 560
RY42
10k
QX52
MC33078M
QX38
TLC2933IPW
VD-D VD-A
RBIAS
VCIN
AG
VIHB
PIHB
NC
NC
VCOO
FI-A
FI-B
PFDO
DG
V
V
LX22
TEM2103T
Clock
output
Inside
Outside
2-8. PLL Circuit (2)
TLC2932IPW (QX42) is used in the PLL circuit. The pin
configuration is shown in Fig. 6-20, the terminal functions
are in table 6-8 and the internal block diagram is shown in
Fig. 6-21.
The circuit diagram of PLL circuit is shown in Fig. 6-23.
The IC is composed of a VCO able to oscillate in 20 – 60
MHz and PFD. In this unit, a rag-read type loop filter is
provided by combining the IC and CRs. The center fre-
quency of VCO varies depending on the constant value of
RX88 and the lock enable frequency is approx. 23 – 40
MHz when the RX88 is 3.3 k
W
.
VHB (pin 10) and PIHB (pin 9) are the terminals to stop
the VCO/PFD operation. To display signal sent from the
personal computer, the IC operation is stopped by making
these terminals Hi.
1
2
3
4
5
6
7
LOGIC V
DD
TEST
VCO OUT
F
IN
-A
F I
N
-B
PFD OUT
LOGIC GND
14
13
12
11
10
9
8
VCO V
DD
R
BIAS
V
COIN
VCO GND
VCO INHIBIT
PFD INHIBIT
NC
Fig. 6-20 Pin configuration of TLC2932IPW
Fig. 6-21 TLC2932IPW internal block diagram
1 5 9 10 14 3 2
7 4 6 12 13 11
LOGIC V
DD
VCO V
DD
VCO OUT
SELECTOR
F
IN
-B
F
IN
-A
PFD
INHIBIT
VCO
INHIBIT
COUNTER
PFD
VCO
LOGIC GND
LPF VCO IN
VCO GND
PFD OUT
R
BIAS
1/2 DIVIDER