Toshiba TLP411E, Technical Training Manual

Page: 41 / 84

6-3
1-2. RGB Signal Input
When the RGB signals are input, sync generation, various
kinds of timing signals generation for liquid crystal panel
driving, and on-screen signal generation are carried out in
the digital circuit. The video signal inputs to the RGB sig-
nal process circuit directly without passing through the digi-
tal circuit. So, each of the A/D converter, field memory
and D/A converter circuit is operating actually, however,
they are not used in practice. And, PLD and PLL circuit (2)
stop their operation. These circuit are used when the video
signal is input.
Fig. 6-2 shows the flow of timing signals when RGB sig-
nals are input. PCLK input to QX45 is a sampling clock as
shown in Fig. 6-2. The oscillation range of the VCO com-
posing of PLL (1) is 40 ~ 85 MHz, so the signal is divided
in 1/2 in the clock divider circuit and used as a PCLK when
a dot clock signal of 20 ~ 40 MHz (VGA system and
SVGA@56 signal) is input. Further, 1/4 clock signal of
VCO oscillation frequency is supplied to SYG (QX32), and
operates SYG.
R SIGNAL
IN
G SIGNAL
IN
B SIGNAL
IN
VD
HD
CLAMP A/D (QX16) BUFFER
BUFFER
BUFFER
A/D (QX17)
CLAMP
CLP PULSE
CLK2 = WCK (1/4 CLK1)
CLK1
PCLK 1
HD (FOR OSD)
HD, VD
1/8 CLK1
1/4 CLK1
CLR
FIOE
WCK (=1/4 CLK1)
WRS, WLRS
1/4 CLK1
INTERNAL
HD
1/3 PCLK, VD
RRS, WLRS
A/D (QX18)
FIELD MEMORY (QX19)
FIELD MEMORY (QX20)
FIELD MEMORY (QX21)
D/A
(QX22)
CLOCK
DIVIDER
(QX39, QX40)
PLL1
(QX38, QX52)
TIMING GENERATOR
FOR LCD PANEL
(QX45)
OSD
(QX43)
TC160G54AF1137
SYG
(QX32)
R SIGNAL
OUT
G SIGNAL
OUT
B SIGNAL
OUT
OSD SIGNALS
(R G B SEL)
TIMING PULSE
FOR
LCD PANEL
BUS SIGNALS
CLAMP
1
VGA, SVGA@56:
SVGA@60~SVGA@85, XGA PCLK=1/2CLK1
PCLK=CLK1
:
EPM7032
PLD
(QX41)
PLL2
(QX42)
Operation stops.
Not used.
40 - 85 MHz
Fig. 6-2 Flow of timing signals when RGB signals are input