Toshiba TLP411E, Technical Training Manual

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4-5
2-7. Sample & Hold Circuit
The block diagram of the circuit is shown in Fig. 4-10 and
its connection diagram is shown in Fig. 4-11. As shown in
the block diagram in Fig. 4-9, 6CH, each consisting of the
level shifter, S/H (sample and hold) and driver circuits, are
contained in CXA2504N.
Each sample & hold operation is carried out on pins 18,
19, 20, 1, 2 & 3 and the re-sample & hold operations for
6CH are carried out together on pins 21 and 40. This means
that the serial data is converted to the parallel data and the
LCD panel operation frequency is lowered.
S/H
16 23
S/H
15 25
S/H 13 27
S/H
8 33
S/H
6 35
S/H S/H
S/H
S/H
S/H
S/H
S/H
5
18
37
19 20 1 2 3 21
40
SH1
SH2
SH3
SH4
SH5
SH6
Drive
Sample & hold
The timings of pins 21
and 40 are the same
as that of SH6.
Re-sample & hold
Fig. 4-9 Sample & hold operation