Toshiba TLP411E Technical Training Manual Download Page 68

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7-6

TDA4665T
(1H DL IC)

Color difference signal

TDA9141

(NTSC/PAL/SECAM)

Sand castle pulse

12 11

16 14

3-2. Video/Color Circuit

The video/color circuit consists of two ICs, TDA9141 (NTSC/

PAL/SECAM DECODER), TDA4665T (BASEBAND DE-

LAY LINE), and supports each system of NTSC, PAL and

SECAM.

Fig. 7-7 shows the pin configuration of TDA9141 and Fig.

7-8 shows the block diagram of TDA9141. Fig. 7-9 shows

the pin configuration of TDA4665T and Fig. 7-10 shows

the block diagram of TDA4665T.

Fig. 7-6

SECAM reference

Second crystal

Reference crystal

CPLL

Filter reference

Analog ground

Y/CVBS in

Cin

HPLL

Fscomb

Address in / CVBS out

-(R-Y)

-(B-Y)

Uin

Vin

SCL

SDA

Supply

Digital supply decoupling

Digital ground

Sand castle

Yout

Vout

Uout

18 F

I / O port

17 CLP / HA

O port / LLC

Fig. 7-7 Pin configuration of TDA9141

Fig. 7-8 Block diagram of TDA9141

Serial data
input/output

Serial clock
input

Horizontal
PLL filter

Sand castle
output

Vertical acquisition
synchronizaotion pulse

Clamping pulse/
H

synchronization

pulse input/output

RED
input

GREEN
input

BLUE
input

Fast switch
select input

Chrominance
U input

Chrominance
voltage input

Chrominance
U output
Chrominance
V output
Luminance output

Chrominance
outputs

SECAM reference
decoupling

Filter reference
decoupling

Reference
crystal input

PLL
loop filter

Second
crystal
input

Comb filter
status input/output

Positive supply

Digital
ground

Analog
ground

Digital
supply
decoupling

Luminance/
CVBS input

Chrominance
input

Output port/
line-locked
clock output

Input/output
port

Address
input
(CVBS output)

I CBUS

INTERFACE

LCA

CHROMINANCE

SWITCH

DELAY

BIAS

TRAP

ACC

SYNC

SEPARATOR

VERTICAL

SYNC

TIMING

GENERATOR

CLP

HORIZONTAL

PLL

TDA9141

MATRIX

SWITCH

IDENTIFI-
CATION

SWITCH

PAL/NTSC
DEMODU-
LATOR

CLOCHE
FILTER

FILTER
TUNING

SECAM
DEMODU-
LATOR

HUE

PLL

CHROMI-
NANCE
BANDPASS

FSC

BUFFER

STM

Summary of Contents for TLP411E

Page 1: ...FIE NO 336 9612 Dec 1996 TECHNICAL TRAINING MANUAL 3 LCD DATA PROJECTOR TLP411U TLP411E ...

Page 2: ...URATION 3 2 SECTION IV RGB DRIVE CIRCUIT 4 1 1 OUTLINE 4 2 2 CIRCUIT DESCRIPTION 4 2 2 1 Level Shifter Q945 Q953 4 2 2 2 Gamma g g g g g Circuit 4 3 CONTENTS 2 3 Level Shifter Circuit Q965 Q968 R1044 4 4 2 4 Black Limiter Q969 Q970 4 4 2 5 Inverted Signal Amplifiers Q974 Q981 4 4 2 6 Switch Circuit Q982 µPD74HC4066A 4 4 2 7 Sample Hold Circuit 4 5 2 8 LCD Panel 4 7 SECTION V MICROCOMPUTER 5 1 1 SY...

Page 3: ... 2 INPUT OUTPUT SIGNAL SWITCH CIRCUIT 7 3 2 1 Audio Video Signal Switch Circuit 7 3 2 2 Input Signals 7 3 3 VIDEO DEMODULATION BLOCK 7 5 3 1 YC Separation Circuit 7 5 3 2 Video Color Circuit 7 6 3 3 Luminance Y Signal Process Circuit 7 7 3 4 Color Signal Process Circuit 7 8 3 5 Picture Sharpness Correction Circuit 7 8 3 6 RGB Demodulation 7 9 3 7 Audio Circuit 7 11 4 RGB SIGNAL PROCESS CIRCUIT 7 1...

Page 4: ...1 1 SECTION I MAIN POWER SUPPLY CIRCUIT ...

Page 5: ...rent protection circuit 6V output detection circuit 6V S6V excesscurrent protection 6V S6V 15 5V over voltage protection Output ON OFF circuit Input rectification circuit Rectification switching circuit Inverter circuit flyback Noise filter circuit Transformer T001 Primary control circuit Secondary rectification smoothing circuit ON OFF control circuit Output ON OFF circuit ON OFF control circuit ...

Page 6: ...the RF001 As a result the rectified current flows into C011 and C012 eliminating the power loss by RF001 in the normal operation state 2 4 Smoothing Rectifying Circuit The input voltage of the unit is set to work in the range of AC100 120V and AC220 240V To keep the AC recti fication output voltage in almost the constant level the voltage doubler rectification is employed for the AC100 120V input ...

Page 7: ... current begins to flow as shown in Fig 1 7 and input voltage is applied to NP winding Fig 1 8 The voltage VNC NC NP x VDC is generated in the NC winding and voltage is supplied to Q001 gate through R018 and C016 At the same time C018 is charged through ZD003 and R020 When the electric potential of C018 rises up to VBE Sat approx 0 7V Q004 is turned on and Q001 is turned off That is ON period of Q...

Page 8: ...control output voltage Fig 1 10 PC002 L101 K A G IC101 R114 R113 VR101 S6V G 2 9 6V S6V 15 5V Overvoltage Protection Circuit As shown in Fig 1 9 the overvoltage of 6V and S6V is detected by ZD101 and the overvoltage 15 5V is de tected by ZD401 When the overvoltage is detected current flows to zener diode the current then flows to PC001 This is transferred to the primary control circuit and trigger...

Page 9: ... as item 2 9 Fig 1 12 2 11 Output ON OFF Circuit 15 5V and 10V outputs can be turned on off by 4 ter minal regulators IC401 and IC201 5V and 6V outputs can be turned on off by POWER MOSS FET Q106 Q302 ON OFF signal is given by the following ON OFF control circuit 2 12 ON OFF Control Circuit This circuit controls the circuit of item 2 11 which de lays the external signal by the integration circuits...

Page 10: ...2 1 SECTION II LAMP HIGH VOLTAGE POWER SUPPLY CIRCUIT ...

Page 11: ...lamp off control signal output When 5V is applied to the ON OFF input in the standby on Q702 FET transistor turns on igniter develops a high voltage pulse 13 to 18 kV and the lamp starts to light up The pulse continues until the lamp turns on for about 1 to 2s But if the lamp does not turn on the OFF output is developed Q702 goes off after the lamp turned on the ig niter circuit stops the operatio...

Page 12: ...3 1 SECTION III OPTICAL SYSTEM ...

Page 13: ...ion light to pass the panel best On the other hand for the P polarization the phase is adjusted so that the P polarization light passes the panel best In this unit when the S polarization characteristic takes effective for the G light component and when the P polarization characteristic takes effective for the R and B light components thus improving the light transmission amount projected from the...

Page 14: ...Incidence side polarized plate Liquid crystal panel 90 rotation Exit side polarized plate Phase difference plate 45 rotation x y 22 5 45 45 22 5 4 3 P polarization light S polarization light No Part name 1 Projection lens 3R Liquid crystal panel red 3G Liquid crystal panel green 3B Liquid crystal panel blue 4 Phase difference plate polarized plate 5 Field lens 9 Mirror box unit 10a f Dichroic mirr...

Page 15: ...rection at each part R B light component a Tilt projection system Screen Reflector Field lens Lamp Liquid crystal panel Projection lens Exit side polarizing direction P polarization light S polarization light Incidence side polarizing direction S polarization light Phase difference plate 45 rotation Incidence side polarized plate Liquid crystal panel 90 rotation Exit side polarized plate Phase dif...

Page 16: ...4 1 SECTION IV RGB DRIVE CIRCUIT ...

Page 17: ... composed of the emitter follower Q945 full feedback unit gain amplifier Q946 Q950 and the current source circuit of sub bright for Q951 Q953 The circuit operates to vary only the DC level of the input signal and develops the signal with only the DC level shifted from the input signal at Q949 The shift level is determined by the current flowing into R976 When a triangular waveform of 2 3V 3 6V sho...

Page 18: ...angu lar waveform of 4 06V 5 36V When the base of Q963 develops 3 55 VDC the emitter of Q961 develops 4 25 VDC In the signal area where the base of Q963 is higher than 4 25V the current of 7 7 mA is flown into R988 because of Q961 turned off and the emitter volt age of Q956 increases by amount of 1 7V 7 7 mA x 220W 1 7V from the base of Q957 As the base voltage of Q957 is close to 4 25V Q961 turns...

Page 19: ...mal input For easy understanding of the op amplifier an op amplifier shown in Fig 4 5 will be refferred Fig 4 5 The output of Q977 is 7V x 1 R1018 R1017 4V 10V so 7V x 1 R1018 R1017 6V 8V is output The constant of R1017 is assumed to 1 kW in considering the internal emitter resistor of Q975 Accordingly the output shown in Fig 4 6 is obtained Fig 4 6 Reverse output operation 2 6 Switch Circuit Q982...

Page 20: ... operation is carried out on pins 18 19 20 1 2 3 and the re sample hold operations for 6CH are carried out together on pins 21 and 40 This means that the serial data is converted to the parallel data and the LCD panel operation frequency is lowered S H 16 23 S H 15 25 S H 13 27 S H 8 33 S H 6 35 S H S H S H S H S H S H S H 5 18 37 19 20 1 2 3 21 40 SH1 SH2 SH3 SH4 SH5 SH6 Drive Sample hold The tim...

Page 21: ... D R S H S H D R Current setting Current setting Level shifter Level shifter Level shifter Level shifter Level shifter Level shifter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 SH4 SH8 SH5 SH6 7 VDC 7 VDC 1 2 VDC 390k 390k 390k CH6 input CH5 input CH4 input CH3 input CH2 input CH1 input 15 5V 12 VDC 5 0V SH1 SH2 SH3 SH7 15 5V 22k 0...

Page 22: ...ngth of 3 3 cm 1 3 type High transparent ratio 20 Built in cross talk free circuit High contrast ratio in normally white mode 200 Standard Built in H V driver Built in input level conversion cir cuit 5V driving possible Up down and left right inversion display function 2 8 2 Element component Number of dots 832 H x 624 V 519 168 Active matrix panel with the driver using multi crystal silicone tran...

Page 23: ...put terminal as shown in Fig 4 13 The area not displayed shaded por tions in Fig 4 13 is written by PSIG signal of pin 1 Fig 4 13 832 624 SVGA MODE MODE1 L MODE2 L MODE3 H 832 624 VGA NTSC MODE MODE1 L MODE2 H MODE3 H 832 624 WIDE MODE MODE1 H MODE2 L MODE3 H 832 624 DISPLAY AREA 832 x 624 Macintosh 16 MODE MODE1 L MODE2 L MODE3 L 832 624 PAL MODE MODE1 L MODE2 H MODE3 L 832 624 PC 98 MODE MODE1 H...

Page 24: ... 18 ENB Enable input terminal for gate selection pulse 7 SIG1 Video signal 1 input terminal to LCD panel 19 VCK Clock input terminal for V shift resistor driving 8 HVDD Power supply input terminal for H driver 15 5V 20 VST Start pulse input terminal for V shift resistor driving 9 RGT Driving direction input terminal for H shift resistor H Normal direction L Reverse direction 21 PCG Uniformity impr...

Page 25: ...5 1 SECTION V MICROCOMPUTER ...

Page 26: ...ocess On screen display process 2 Normal control Power ON OFF Input switch Sound volume control UP DOWN Menu UP DOWN Mute ON OFF Display ON OFF Adjusting value reset Focus UP DOWN Zoom UP DOWN 3 Adjustment control Video controls high low brightness ratio brightness color density tint sharpness Panel adjustments V position H position phase clock Projection adjustments Front projection front project...

Page 27: ...E SYNC MODE PL003 FAN PW 14 15 CXA1315M F REM R REM LED KEY PL006 FAN1 ER PL006 FAN1 SW PL008 FAN2 SW LAMP PW AMP ER P502 CAMON ZL001 TEMP ER MAIN ER FAN ER GAIN CONTRAST BRIGHT VIDEO RGB P501 P901 SCL SDA S 6V OSL OSC OSD SYL SYC SYD TGL TGC TGD TX RX VD MAIN SW PL005 P500 M62358FP HC595AF HC165AF HC165AF 3 3 3 3 15 8 3 3 2 3 2 3 6 8 3 2 3 2 5 4 4 2 QL09 QL08 QL05 MAX232CPE HC14AF 3 4 5 QL03 CAT2...

Page 28: ... O 41 A7 Address for external ROM O 10 SWD HC595 data O 42 A6 Address for external ROM O 11 STL HC165 load O 43 A5 Address for external ROM O 12 STC HC165 clock O 44 A4 Address for external ROM O 13 STD HC165 data I 45 A3 Address for external ROM O 14 TX RS 232C transmission data O 46 A2 Address for external ROM O 15 RX RS 232C reception data I 47 A1 Address for external ROM O 16 VD Vertical flyba...

Page 29: ...ll the adjustment data are read out by the system microcomputer QL01 at the tim ing shown in the read out timing diagram of Fig 5 3 A thereby realizing the previous status When saving the data all the adjustment data are written by the system microcomputer QL01 at the timing shown in the timing diagram of Fig 5 3 B thereby keeping the current status However if a failure such as power interruption ...

Page 30: ...l signal reception timing diagram 6 RS 232C TRANSMIT RECEIVE PROCESS In the RS 232C transmit receive process an RS 232C sig nal entered through the RS 232C connector D SUB 9P on the rear panel is decoded in the RS 232C interface QL05 MAX232CPE and fed to the system microcom puter QL01 through PL005 Fig 5 5 shows the RS 232C signal timing diagram Fig 5 5 RS 232C signal timing diagram 5V 0V 10V 10V ...

Page 31: ...ays the status Fig 5 7 shows the data display timing diagram Table 5 3 shows the contents of the status display signals and the logic SWL SWC SWD H G F E D C B A Fig 5 7 Data display timing diagram Signal name A B C D E F G H Pin No 11 12 13 14 3 4 5 6 QL11 ON STANDBY MENU DOWN MENU UP VOL ADJ VOL ADJ INPUT AUX1 AUX2 L ON ON ON ON ON ON ON ON H OFF OFF OFF OFF OFF OFF OFF OFF QL12 FAN1 ER FAN1 SW ...

Page 32: ...and A 2 byte continuous command First byte Second byte First byte Second byte Second byte Fig 5 8 Timing diagram for on screen control signals 10 VIDEO MODE FETCH PROCESS In the video mode fetch process a status fetch IC Q543 CXA1315M fetches the status in the read mode of I2C bus Custom 45 Fig 5 9 shows the I2C bus read timing diagram Table 5 4 shows the contents of the video mode signals and the...

Page 33: ...D0 START SDA SCL 1 2 7 8 9 ACK 1 2 7 8 9 ACK 1 2 7 8 9 ACK STOP Slave address Sub address Data Part No Type name Contents of process Q540 CXA1315M Custom 42 Brightness contrast RGB gain Video RGB input switching Q200 TA1218N Custom 90 Input signal Video Audio Video S terminal input Q201 TC9090N Custom 8A Color signal process 3D Y C separation Q220 TDA9141 Custom 8A Sync detection process Custom 8B...

Page 34: ... 5 12 CXD2442Q control bus timing diagram Fig 5 14 SYG write mode bus timing diagram Fig 5 13 SYG read mode bus timing diagram TGL TGC TGD D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Part No Type name Contents of process Q1038 Q1039 M62358FP Panel drive process QX45 CXD2442Q Screen position control V position H position sample phase Panel display control Projection attribution etc QX32 SYG TC1...

Page 35: ...range After this the lamp can be turned on again by the STANDBY ON key 4 Moreover the fan works for about 2 min to lower temperature of the unit For this period the main power is kept turning on 5 When the main power turns off the fan also stops and returns to the standby status If an error occurs due to some causes the STANDBY ON LED turns on in red and the error information is kept in the displa...

Page 36: ...70 VGA 70 Hz 640 350 800 450 31 470 70 020 28 322 P N O V70 VGA 70 Hz 640 400 800 450 31 470 70 020 28 322 N P O V72 VGA 72 Hz 640 480 832 520 37 860 72 810 31 500 N N O V75 VGA 75 Hz 640 480 840 500 37 500 75 000 31 500 N N O V85 VGA 85 Hz 640 350 832 445 37 861 85 080 31 500 P N O V85 VGA 85 Hz 640 400 832 445 37 861 85 080 31 500 N P O V85 VGA 85 Hz 720 400 936 446 37 927 85 039 35 500 N P V85 ...

Page 37: ...ting condi tions or a non acknowledgment signal NAK 16h is out put without the operating condition Nothing is output if reception terminates abnormally When sending a command leave the interval for at least 100 ms Moreover a longer process time is necessary at the power on or off and input switching so take care to leave a sufficient interval Pin No Signal name Signal content I O 2 RXD Receive dat...

Page 38: ...ve SAVE DATA by menu by menu SAV Adjustment value saving Standard PRESET DATA by menu by menu PRE Adjustment value standard setting Contrast ratio CONTRAST by menu by menu VCN Contrast Brightness BRIGHT by menu by menu VBR Brightness Density COLOR by menu by menu VCL Color Hue TINT by menu by menu VTN Tint Picture quality SHARP by menu by menu VSH Sharpness V position V POS by menu by menu SPV Ver...

Page 39: ...6 1 SECTION VI DIGITAL CIRCUIT ...

Page 40: ...s owing to the input signal and the area not displayed is masked The masked area is generated by writing the mode signal for the liquid crystal panel during the blanking pe riod Accordingly the signal supplied to the liquid crystal panel is a usual non interlace signal and any blanking period is not added For more details refer to item 2 8 in section 4 Page 4 7 R SIGNAL IN G SIGNAL IN B SIGNAL IN ...

Page 41: ... so the signal is divided in 1 2 in the clock divider circuit and used as a PCLK when a dot clock signal of 20 40 MHz VGA system and SVGA 56 signal is input Further 1 4 clock signal of VCO oscillation frequency is supplied to SYG QX32 and operates SYG R SIGNAL IN G SIGNAL IN B SIGNAL IN VD HD CLAMP A D QX16 BUFFER BUFFER BUFFER A D QX17 CLAMP CLP PULSE CLK2 WCK 1 4 CLK1 CLK1 PCLK 1 HD FOR OSD HD V...

Page 42: ...ided clock signal generated in the PLL 1 And in the enlargement mode the clock signal generated is 2 5 times Fig 6 3 shows the operation when NTSC signal is input 1 4 PAL SECAM Signal Input The vertical effective line number for PAL signal is 575 lines and this displays a picture in 762 x 572 pixels area When PAL signal is displayed the enlargement and WIDE modes are not available The basic operat...

Page 43: ...lamped to fit the reference level of the A D converter The clamp is of a pedestal clamp type and uses the reference level voltage of A D converter The ac tual clamp voltage potential is approx 1 2V Fig 6 4 shows the clamp circuit for G signal section Fig 6 4 Clamp circuit diagram 2 2 A D Converter Either CXD1175AM manufactured by SONY or TLC5510INS manufactured by TI is used forA D converter QX16 ...

Page 44: ...nable terminal OE L level data enable OE H level output high impedance 2 24 DGND Digital GND terminal 3 10 D1 D8 Data otput terminal D1 LSB D8 MSB 11 13 VDDD Digital power supply terminal 12 CLK Clock input terminal 16 VRTS Reference voltage output terminal upper Short circuit to VRT when using internal reference voltage Develops 2 63V 17 VRT Reference voltage input terminal upper 23 VRB Reference...

Page 45: ...gister x 8 x 8 D in D out WE OE Memory array 1152 dot x 288 line x 8 1 1024 dot x 324 line x 8 1 10368 dot x 32 word x 8 1 WCK CGW WRS WAS WAD WLRS WWND WCLR RCK CGR RRS RAS RAD RLRS RWND RCLR Write counter Read counter Memory controller Refresh counter Note 1 Selected by the mode pin Table 6 2 HM530281RTT 20 pin configuration Pin No Name Function Pin No Name Functions 1 8 DIN0 7 Data input 22 25 ...

Page 46: ...ent line and the line increment reset which goes forward to the head of the next line are pro vided other than the normal reset which jumps to the upper left address of the screen Refer to Fig 6 9 These reset functions are controlled by the signal devel oped from pins 30 RLRS 31 RRS and 14 WRS Table 6 4 shows the relation of each reset terminal and reset func tion The write control to the memory i...

Page 47: ...the interlace signal into non interlace signal The line being read twice repeatedly is changed by ODD EVEN of the field in order to correct the center of the interlace signal In the enlargement mode after resetting the memory the line hold operation once between the line increment opera tions and the line hold operation twice between the line increment operations are carried out alternately The op...

Page 48: ...AG H Operation Operation Operation Operation RRS RESET HOLD INC HOLD HOLD HOLD INC INC INC RESET INC HOLD INC INC INC HOLD HOLD HOLD RESET INC HOLD INC INC INC HOLD HOLD HOLD RESET INC HOLD HOLD HOLD HOLD INC INC HOLD RE 1H RLRS RRS RLRS RRS RLRS RRS RLRS Input signal Output signal Fig 6 12 Memory control signal timing diagram ...

Page 49: ...LKG I G channel clock signal input terminal 3 CLKB I B channel clock signal input terminal 4 11 R1 R8 I R channel data signal input terminal R1 MSB R8 LSB 14 21 G1 G8 I G channel data signal input terminal G1 MSB G8 LSB 24 31 B1 B8 I B channel data signal input terminal B1 MSB B8 LSB 34 VCCD Digital power supply terminal 5V 41 44 47 VCCA Analog power supply terminal 5V 48 D GND Digital ground term...

Page 50: ... MO5 MO4 MO3 MO2 MO1 MO0 CX33 16V 0 33 CX34 16V 0 33 CX32 16V 0 33 LX13 TEM2103T LX12 TEM2103T CX29 16V 0 33 CX30 16V 0 33 CX31 16V 0 33 RX37 100 RX38 100 RX39 100 RX40 560 RX41 560 RX42 560 RX43 560 RX44 560 RX45 560 QX23 2SC4116Y QX24 2AC4116Y QX25 2SC4116Y LX15 TEM2011Y CX36 16V 1 PY08 DAGND QX26 TA78L05F CX37 16V 1 IN OUT GND 9V 9V ZX11 TEM1043 ZX10 TEM1043 ZX12 TEM1043 RX46 560 RX48 560 QX29 ...

Page 51: ...nerated in the PLL circuit 1 divided in four and the clock signal generated in PLL circuit 2 with the serial bus setting When a signal is sent from a personal computer the clock signal from PLL circuit 1 is used and when a NTSC PAL signal is sent the clock signal from PLL circuit 2 is used In the sync signal measurement section a HD signal fre quency input to pin 134 and line number for 1 field is...

Page 52: ...pply terminal for internal logic circuit PFD section I O section Desirable to be separated from power supply voltage supply terminal for VCO completely 2 TEST Used at test Connect to GND at normal operation 3 VCO OUT VCO output terminal Fixed to L level at inhibit 4 5 FIN A FIN B Input terminal for reference frequency input fREF IN and comp signal dividing VCO output by external counter Input fREF...

Page 53: ... Fig 6 23 The IC is composed of a VCO able to oscillate in 20 60 MHz and PFD In this unit a rag read type loop filter is provided by combining the IC and CRs The center fre quency of VCO varies depending on the constant value of RX88 and the lock enable frequency is approx 23 40 MHz when the RX88 is 3 3 kW VHB pin 10 and PIHB pin 9 are the terminals to stop the VCO PFD operation To display signal ...

Page 54: ...and frequency from the external counter Normally fREF IN is input at FIN A terminal and the frequency from the external counter that is divided multiplied is input at FIN B terminal 6 PFD OUT PFD output terminal It can be fixed at high impedance 7 LOGIC GND GND terminal for internal logic circuit 8 N C Internal unconnected terminal 9 PFD INHIBIT PFD inhibit function control terminal 10 VCO INHIBIT...

Page 55: ...CLR BLK HCK2 HCK1 HST MODE1 MODE2 VSS MODE3 XRGT RGT VDD SH8 SH7 SH6 SH5 SH4 VSS SH3 HDN VSS CK12 HSYNC VSYNC PEO PWM FPD RPD CKO1 CKI1 VSS TC SCTR SCLK SDAT VSS TST1 TST2 TST3 TST4 TST5 VSS VDD CKLIM CXD2442Q Fig 6 23 Pin configuration of CXD2442Q Table 6 9 CXD2442Q pin function Pin No Name I O Functions 1 HDN O Pulse output for phase comapration 2 VSS GND 3 CK12 I Colck input terminal VGA 4 HSYN...

Page 56: ...rity 40 SH2 O Sample and hold pulse 2 output For high withstanding voltage SH positive polarity 41 SH3 O Sample and hold pulse 3 output For high withstanding voltage SH positive polarity 42 VSS GND 43 SH4 O Sample and hold pulse 4 output For high withstanding voltage SH positive polarity 44 SH5 O Sample and hold pulse 5 output For high withstanding voltage SH positive polarity 45 SH6 O Sample and ...

Page 57: ...e buffer Negative polarity 69 RCK O Read clock output For high speed line buffer 70 RSTW O Reset write output For high speed line buffer Negative polarity 71 WCK O Write clock output High speed line buffer 72 VSS GND 73 VDD Power supply 74 XCLR I System clear terminal L all clear 75 PRE I Preset terminal L Preset to Macintosh 17 mode 76 TST9 Test terminal Open when used 77 TST10 Test terminal Open...

Page 58: ...OUNTER AUX VD COUNTER DECODER PLL COUNTER DECODER PULSE ELIMINATOR FIELD LINE CONTROLLER DECODER V TIMING PULSE GENERATOR DECODER V TIMING PULSE GENERATOR V SYNC SEPARATOR V RESET PULSE GENERATOR V POSITION COUNTER CK12 CKLIM CK11 CK01 HYSNC VSYNC BLK VCK VST FLDI FLDO FRP XFRP TST1 TST2 TST3 TST4 TST5 TST6 TST7 TST8 TST9 TST10 PCG ENB CLR HCK2 HCK1 HST SH8 SH7 SH6 SH5 SH4 SH3 SH2 SH1 SHD4 SHD3 SH...

Page 59: ...inverted at L Pulse SH1 2 and 3 are replaced to SH4 5 and 6 SH1 is replaced with SHD3 Upper third line BLK of the timing chart is not an actual pulse output from the terminal The pulse is drawn as temporary pulse to create the chart RSTW RCK RSTR BLK FRP PCG PRG VCK ENB CLR SHD4 LCX016 SVGA 800x600 RGT H PLLP LHHHHHLLHLH LSB HP HHHLHLLL LSB HDNP LLLLL LSB SHP LLLLLLL LSB HCKP LLLL LSB HSTP LH LSB ...

Page 60: ...H reverse HST ENB XCLP1 XCLP2 PCG PRG CLR FRP 1F reverse FLDO BLK 594 600 1 12 10 20 30 37 Note DWN VST is inverted at L Upper fifth line BLK of the timing chart is not an actual pulse output from the terminal The pulse is drawn as temporary pulse to create the chart FRP FCDO polarity for 1H and 1V frequency is not specified Fig 6 26 Example of timing signal 2 ...

Page 61: ...12 10 11 HSYNC VSYNC RBLK GBLK RBLK VCBL VB VG VR VMON BUSY CLK CS DATA PCL VDD CKOUT OSCOUT OSCIN VSS GND Data input shift register Data buffer register Instruction decoder Control signal VDD VSS PCL Character size register H address register Writing address counter H address counter H position counter H size counter Video RAM Charactor data 8 bitX208 word Color data 3 bitX208 word Printer data 1...

Page 62: ...KOUT Clock out terminal Inverted output for OSC OUT 20 Hsync Horizontal sync signal input terminal Dot clock signal oscillator oscillates at signal rising period and sync Hi level 19 Vsync Vertical sync signal input terminal Input sync negative 12 13 14 VR VG VB Character signal output terminal Character signal output terminal corresponding to RGB signals Signal output Positive 15 VCBL Composite b...

Page 63: ...7 1 SECTION VII VIDEO SIGNAL PROCESS CIRCUIT ...

Page 64: ...ircuit provided in a later stage through the switching circuits The sync signal is corresponding to HD VD composite sync CS and SYNC ON G signals The sync signal en tered is separated into a HD and VD and waveform shaped in the sync separation IC 1 4 Audio Signal Amplification Block Audio signal inputs are corresponding to L and R stereo inputs on the video and RGB inputs The signals are output to...

Page 65: ...signals input from S terminal are input to pins 12 and 14 respectively 2 2 3 Camera Signal The video signal sent from the camera section is supplied as Y C signal and input to pins 16 and 18 The video signal finally selected is output from pins 34 C and 36 Y respectively and supplied to the signal process ing section in the later stage At the same time the same video signal as the finally selected...

Page 66: ...28 38 42 36 30 34 32 24 25 27 19 20 21 22 41 40 37 1 2 39 35 Det select Det in V1 in V2 in TV in S1 Y V in S2 Y V in C1 in C2 in Sync out LS1 in LS2 in LV1 in LV2 in LTV in RS1 in RS2 in RV1 in RV2 in RTV in Vcc GND V out 1 V out 2 Y out YI in C out CI in SCL SDA Address I O 1 3 value I O 2 3 value I O 3 O 4 O 5 Lout TV L out L out 2 R out TV R out 1 R out 2 Vcc GND 26 Fig 7 3 Internal block diagr...

Page 67: ...TEST2 Test terminal 13 KILLER Clock killer switch 14 PLLSEL Selection input clock 15 VDD3 Digital VDD 16 VSS3 Analog GND 17 VSS2 PLL GND 18 VDD2 PLL VDD 19 CKIN Clock input 20 VFIL VCO filter 21 2 1 VDD Line memory bias 22 BIAS3 DAC bias 23 COUT C output 24 BIAS2 DAC bias 25 YOUT Y output 26 VREF1 DAC bias 27 VDD4 DAC VDD 28 VSS4 DAC GND Fig 7 4 Pin configuration of TC9090AN Table 7 1 Terminal fun...

Page 68: ... 8 Block diagram of TDA9141 Serial data input output Serial clock input Horizontal PLL filter Sand castle output Vertical acquisition synchronizaotion pulse Clamping pulse HA synchronization pulse input output RED input GREEN input BLUE input Fast switch select input Chrominance U input Chrominance voltage input Chrominance U output Chrominance V output Luminance output Chrominance outputs SECAM r...

Page 69: ...ers as follows depending on type of the signal entered a For a SECAM input it passes through a burst signal trap circuit b For a NTSC PAL with burst signal input YC sepa rated signals the burst signal trap circuit is bypassed It passes through a delay circuit for a phase match ing to the color signal c For a NTSC PAL without burst signal input above trap circuit and the delay circuit are bypassed ...

Page 70: ...h the delay circuit Amount of the delay can be set to any value between 20ns and 1100ns to the color difference signals Picture sharpness correction frequency can be selected ei ther one of 2 6 MHz and 5 MHz In this unit the amount of delay is set to 90ns and the picture sharpness correction frequency is set to 2 6 MHz GND1 SAND REF SCL C CLP2 C CLP1 C COR C N C SDA P V DL C MED757 TDA4672 i Y V o...

Page 71: ...astle pulse I2 C EBUS 100nF SDA SCL V 5V to 8V P 100nF V REF GENERATION V REF CORING CORING I2 C EBUS BLACK LEVEL CLAMP 100nF I2 C EBUS PEAKING Y R Y B Y TDA4672 1 0 5 0 5 Peaking frequency 5 MHz 2 6MHz 5 MHz 2 6 MHz Coring on off Sand castle 5V 12V I2 C EBUS RECEIVERS REF V 100 ns 90 ns 100 ns 90 ns 45 ns 90 ns 180 ns BLACK LEVEL CLAMP 180 ns 450 ns R Y B Y 100nF 100nF REF V Y 100nF REF V Control...

Page 72: ...L REGISTERS SC5 YHI DELOF FSBL HDTV YEXH BCOF RELC TCPL NMEN FSON1 FSDI51 FSON2 FSDI52 8 DATA 6 DATA REGISTERS DIGITAL ANALOG CONVERTERS F SBL NMEN HDTV BLANK MP TIMING GENERATOR CL HV H SC5 DELOF BREN I 2 C BUS RECEIVER SCL SDA I C bus 2 Sand castle input SC 330nF Leakage storagee UGAP 220nF 220nF 220nF LEAKAGE CURRENT COMPARATOR 1ST AND 2ND SWITCH ON DELAY CUT OFF CONTROL Leakage and cut off cur...

Page 73: ...s amplified by 6 dB 75W drive for RGB outputs The RGB output signals are always developed as long as signals are being supplied to the RGB input terminal The sync signal is corresponding to HD VD CS compos ite sync and SYNC ON G The HD VD CS are connected to the sync separation IC Q537 M52346SP through a buffer Q512 74HCT240AF and RGB output terminals Sync separation priority is HD VD CS and SYNC ...

Page 74: ... B SUB CONTRAST B GND2 B CP IN OSD IN R VCC1 G SUB CONTRAST G GND2 G INPUT B OSD IN B MAIN CONTRAST OUTPUT R HOLD R GND2 R GND2 B OUTPUT R HOLD B SUB OSD ADJUST G VCC2 G HOLD G GND2 G NC VCC2 R VCC2 B Fig 7 18 µPD74HC4066A Pin 5 Pin 6 Video input LOW HIGH RGB input HIGH LOW The control items of the IC are five items main contrast sub contrast for each RGB and brightness The actual con trol is carr...

Page 75: ...ence and polarity information is shown in tables 7 6 and 7 7 Table 7 6 Q540 CXA1315M Fig 7 19 Pin 3 R sub contrast Pin 4 G sub contrast Pin 5 B sub contrast Pin 6 Main contrast Pin 7 Brightness Pin 1 RGB Video SW control signal Pin 2 RGB Video SW control signal Pin 9 RGB Video sync SW control signal Pin 2 Pin 1 Pin 9 Video input 1 0 0 RGB input 0 1 1 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 SW1 SW0 ...

Page 76: ... M52346SP Input status Q543 CXA1315 Pin 6 HD COMP Pin 8 VD SW0 2 SW1 1 SW2 9 SW3 0 HD COMP POS NON H H L H HD COMP POS VD POS H H L L HD COMP POS VD NEG L H L L HD COMP NEG NON H L L H HD COMP NEG VD POS H L L L HD HD COMP NEG VD NEG L L L L NON NON H H H H NON VD POS H H H L NON VD NEG L H H L Q537 M53346SP output terminal V POL 19 H POL 18 H STATE 1 V STATE 2 ...

Page 77: ...8 1 SECTION VIII CCD CAMERA CIRCUIT ...

Page 78: ...the gamma process is carried out the signal enters the encoder IC QL03 through 1H delay IC QL04 In the encoder IC QL03 the horizontal contour signal generated in DL ZL04 and the vertical contour signal sent from the process IC QL02 are mixed with luminance signal and added to the sync signal The mixed signal is output as a Y signal through 75W driver QL08 The color signal S1 S2 also enters the pro...

Page 79: ...CCD OPT LPF QJ05 QJ02 QJ01 LENS IH LPF Y11 QL04 ZL03 ZL01 ZL02 S1 S2 QL01 QL02 V DRIVER AGC QJ14 CDS CXO ZJ01 QJ03 QJ13 ZL04 8fsc GATE GATE POWER1 POWER2 UP DOWN UP DOWN MOD MOD H AP QL03 QL07 QL08 BPF 19V QK02 QK08 QK01 15 5V 9V 5V TPL5 C C Y EE To PJ01 Pin 5 To PJ02 Pin 2 To PJ02 Pin 4 NTSC Y SUPRESS DL DET W C SET IUP QJ04 S H SLICE S H S H QJ15 QM11 ...

Page 80: ...9 1 SECTION IX FLUORESCENT LAMP INVERTER CIRCUIT ...

Page 81: ...voltage at QM03 VBE DM05 and DM06 are connected in series to prevent the overheat at short circuiting When the resistor value of RM02 is small heat generation of QM03 lowers However if the value is too small the current of DM03 DM05 and DM06 in continuity becomes large DM04 increases only the base current of QM03 when it turns on and reduces the VCD sat of QM03 to lower the heat generation RM07 wo...

Page 82: ...s a ON OFF switch for the camera power supply When pin 10 of SM01 develops L the power is supplied to the camera The waveforms of each section at operation is shown in Figs 9 3 and 9 4 Fig 9 3 Fig 9 4 30V 80V 0V 0 22A 0 16A 0 70 kHz Fluorescent lamp voltage Fluorescent current 2 TROUBLESHOOTING 2 1 Fluorescent does not turn on OK OK NO NG YES NO YES Replace fluorescent lamp 12V between pins 13 and...

Page 83: ...9 4 3 CIRCUIT DIAGRAM Fig 9 5 Cicuit diagram ...

Page 84: ...TOSHIBA AMERICA CONSUMER PRODUCTS INC NATIONAL SERVICE DIVISION 1420 B TOSHIBA DRIVE LEBANON TENNESSEE 37087 ...

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