59
SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Applications, Implementation, and Layout
Copyright © 2011–2020, Texas Instruments Incorporated
7.2
System Design
7.2.1
Layout Considerations
Keep all decoupling capacitors as close to the IC as possible, with the high-frequency decoupling
capacitors (10 nF) closer than the low-frequency decoupling capacitors (2.2 µF).
Place ground vias as close as possible to the ground side of the capacitors and reader IC pins to minimize
any possible ground loops.
It is not recommend using any inductor sizes below 0603 as the output power can be compromised. If
smaller sized inductors are absolutely necessary, the designer must confirm output performance.
Pay close attention to the required load capacitance of the used crystal and adjust the two external shunt
capacitors accordingly. Follow the recommendations of the crystal manufacturer for those values.
There should be a common ground plane for the digital and analog sections. The multiple ground sections
or "islands" should have vias that tie the different sections of the planes together.
Ensure that the exposed thermal pad at the center of the IC is properly laid out. It should be tied to ground
to help dissipate heat from the package.
Trace line lengths should be minimized whenever possible, particularly the RF output path, crystal
connections, and control lines from the reader to the microprocessor. Proper placement of the TRF7963A,
microprocessor, crystal, and RF connection/connector help facilitate this.
Avoid crossing of digital lines under RF signal lines. Also, avoid crossing of digital lines with other digital
lines whenever possible. If the crossings are unavoidable, 90° crossings should be used to minimize
coupling of the lines.
Depending on the production test plan, the designer should consider possible implementations of test
pads or test vias for use during testing. The necessary pads and vias should be placed in accordance with
the proposed test plan to help enable easy access to those test points.
If the system implementation is complex (for example, if the RFID reader module is a subsystem of a
larger system with other modules such as
Bluetooth
®
, Wi-Fi
®
, microprocessors, and clocks), special
considerations should be taken to ensure that there is no noise coupling into the supply lines. If needed,
special filtering or regulator considerations should be used to minimize or eliminate noise in these
systems.
For more information and details on layout considerations, see the
.
7.2.2
Impedance Matching TX_Out (Pin 5) to 50
Ω
The output impedance of the TRF7963A when operated at full power out setting is nominally 4 + j0
Ω
(4
Ω
real). This impedance must be matched to a resonant circuit, and TI recommends a matching circuit from
4
Ω
to 50
Ω
, as commercially available test equipment (for example, spectrum analyzers, power meters,
and network analyzers) are 50-
Ω
systems. See
and
for an impedance match
reference circuit. This section explains how the values were calculated.
Starting with the 4-
Ω
source,
and
shows the process of going from 4
Ω
to 50
Ω
by
showing it represented on a Smith Chart simulator (available from
http://www.fritz.dellsperger.net/
). The
elements are grouped together where appropriate.
