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SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Detailed Description
Copyright © 2011–2020, Texas Instruments Incorporated
6.14.1.5 FIFO Control Registers
6.14.1.5.1 FIFO Status Register (0x1C)
describes the bit fields of the FIFO Status register. This register contains the low nibbles of the
complete bytes to be transferred through the FIFO and information about a broken byte and the number of
bits to be transferred from it.
Table 6-37. FIFO Status Register (0x1C)
BIT NO.
BIT NAME
FUNCTION
DESCRIPTION
B7
RFU
B7 = 0
Reserved for future use (RFU)
B6
Fhil
FIFO level high
Indicates that 9 bytes are already in the FIFO (for RX) (also see
register 0x0C bit 5)
B5
Flol
FIFO level low
Indicates that only 3 bytes are in the FIFO (for TX) (also see register
0x0C bit 5)
B4
Fove
FIFO overflow error
Too many bytes were written to the FIFO
B3
Fb3
FIFO bytes fb[3]
Bits B0:B3 indicate how many bytes that are loaded in FIFO were
not read out yet (displays N – 1 number of bytes). If 8 bytes are in
the FIFO, this number is 7 (also see register 0x0C bit 6).
B2
Fb2
FIFO bytes fb[2]
B1
Fb1
FIFO bytes fb[1]
B0
Fb0
FIFO bytes fb[0]
6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
describes the bit fields of the TX Length Byte1 register. This register contains the high two
nibbles of complete intended bytes to be transferred through FIFO.
Default Value:
0x00, set at POR and EN = 0. The register is also automatically reset at TX EOF.
Table 6-38. TX Length Byte1 Register (0x1D)
BIT NO.
BIT NAME
FUNCTION
DESCRIPTION
B7
Txl11
Number of complete byte bn[11]
High nibble of complete intended bytes to be transmitted
B6
Txl10
Number of complete byte bn[10]
B5
Txl9
Number of complete byte bn[9]
B4
Txl8
Number of complete byte bn[8]
B3
Txl7
Number of complete byte bn[7]
Middle nibble of complete intended bytes to be transmitted
B2
Txl6
Number of complete byte bn[6]
B1
Txl5
Number of complete byte bn[5]
B0
Txl4
Number of complete byte bn[4]
