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EXAMPLE STENCIL DESIGN

32X (0.6)

32X (0.25)

28X (0.5)

(4.8)

4X (

1.49)

(0.845)

(R0.05) TYP

VQFN - 1 mm max height

RHB0032E

PLASTIC QUAD FLATPACK - NO LEAD

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

SYMM

METAL
TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

Summary of Contents for TRF7963A

Page 1: ...he reader is configured by selecting the desired protocol in the control registers Direct access to all control registers allows fine tuning of various reader parameters as needed The TRF7963A device...

Page 2: ...rogrammable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional external circuits within the reader system To evaluate the latest products in the TRF79xx product family TR...

Page 3: ...Functional Block Diagram 11 6 2 Power Supplies 11 6 3 Supply Arrangements 12 6 4 Supply Regulator Settings 13 6 5 Power Modes 14 6 6 Receiver Analog Section 17 6 7 Receiver Digital Section 18 6 8 Osc...

Page 4: ...2020 Texas Instruments Incorporated 2 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from May 18 2017 to March 11 2020 Page Remov...

Page 5: ...Connect more with the industry s broadest wireless connectivity portfolio Products for NFC RFID TI provides one of the industry s most differentiated NFC and RFID product portfolios and is your solut...

Page 6: ...ated supply 2 7 V to 5 V normally connected to VDD_PA pin 4 4 VDD_PA INP Supply for PA normally connected externally to VDD_RF pin 3 5 TX_OUT OUT RF output selectable output power 100 mW or 200 mW wit...

Page 7: ...I O_7 BID I O pin for parallel communication MOSI for serial communication SPI 25 EN2 INP Selection of power down mode If EN2 is connected to VIN then VDD_X is active during power down mode 2 for exa...

Page 8: ...device 5 Specifications 5 1 Absolute Maximum Ratings 1 over operating free air temperature range unless otherwise noted 2 MIN MAX UNIT Input voltage range VIN 0 3 6 V Maximum current IIN 150 mA Maximu...

Page 9: ...ply current without antenna driver current Oscillator regulators RX and AGC are active TX is off 10 5 14 mA ION2 Supply current in TX half power Oscillator regulators RX AGC and TX active POUT 100 mW...

Page 10: ...ck depends on the capacitive load Maximum SPI clock speed should not exceed 10 MHz This clock speed is acceptable only when external capacitive load is less than 30 pF MISO driver has a typical output...

Page 11: ...d Description Copyright 2011 2020 Texas Instruments Incorporated 6 Detailed Description 6 1 Functional Block Diagram Figure 6 1 shows the functional block diagram Figure 6 1 Functional Block Diagram 6...

Page 12: ...e used per reference schematics When configured for 3 V manual operation the VDD_A output can be set from 2 7 V to 3 4 V in 100 mV steps see Table 6 2 NOTE The configuration of VDD_A and VDD_X regulat...

Page 13: ...is VSS pin 10 the analog negative supply is VSS_A pin 15 the logic negative supply is VSS_D pin 29 the RF output stage negative supply is VSS_PA pin 6 and the negative supply for the RF receiver VSS_...

Page 14: ...x 0 0 0 VDD_RF 2 7 V VDD_A 2 7 V VDD_X 2 7 V The regulator configuration function adjusts the regulator outputs by default to 250 mV below VIN level but not higher than 5 V for VDD_RF 3 4 V for VDD_A...

Page 15: ...E Mode 4 full power 5 VDC x 1 21 07 On On On x On 130 23 20 to 25 s Mode 4 full power 3 3 VDC x 1 20 07 On On On x On 67 18 Mode 3 half power 5 VDC x 1 31 07 On On On x On 70 20 20 to 25 s Mode 3 half...

Page 16: ...ce the reader stays active If the EN input is not set high EN 0 within 100 s after the SYS_CLK output is switched from auxiliary clock 60 kHz to high frequency clock derived from the crystal oscillato...

Page 17: ...he default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver To determine the signal quality the response from the tag is detected by the main pin RX_...

Page 18: ...start of frame SOF end of frame EOF start of communication and end of communication are automatically removed The parity bits and CRC bytes are also checked and removed The end result is clean or raw...

Page 19: ...il the start of tag response If there is no tag response in the defined time an interrupt request is sent and a flag is set in the IRQ Status register 0x0C This enables the external controller to be r...

Page 20: ...the communication to the Tag this means the TX must be on Bit 1 in the Chip Status Control register 0x00 defines if internal RSSI or the external RSSI value is stored in the RSSI Levels and Oscillator...

Page 21: ...ntrolled by the Chip Status Control register 0x00 and the EN and EN2 signals The oscillator generates the RF frequency for the RF output stage and the clock source for the digital section The buffered...

Page 22: ...the modulation type ASK or OOK at pin 12 External control of the modulation type is made possible only if enabled by setting B6 in the Modulator and SYS_CLK Control register 0x09 to 1 In normal opera...

Page 23: ...443B TX Options register 0x02 It controls the SOF and EOF selection and EGT selection for the ISO IEC 14443 B protocol ISO14443A High Bit Rate and Parity Options register 0x03 This register enables th...

Page 24: ...terrupt IRQ interrupt IRQ interrupt Communication is initialized by a start condition which is expected to be followed by an Address Command word Adr Cmd The Adr Cmd word is 8 bits long and Table 6 7...

Page 25: ...011 REVISED MARCH 2020 Submit Documentation Feedback Product Folder Links TRF7963A Detailed Description Copyright 2011 2020 Texas Instruments Incorporated The following examples show the expected comm...

Page 26: ...ts the format of a continuous address register read and Figure 6 5 and Figure 6 6 show examples Table 6 8 Continuous Address Mode Start Adr x Data x Data x 1 Data x 2 Data x 3 Data x 4 Data x n StopCo...

Page 27: ...ed Table 6 9 lists the format of a single address register read and Figure 6 7 and Figure 6 8 show examples Table 6 9 Noncontinuous Address Mode Single Address Mode Start Adr x Data x Adr y Data y Adr...

Page 28: ...t keeps track of the number of bytes loaded into the FIFO If the number of bytes in the FIFO is n the register value is n 1 number of bytes in FIFO register If 8 bytes are in the FIFO the FIFO counter...

Page 29: ...data or remove the data as necessary The MCU also checks the number of data bytes to be sent so as to not surpass the value defined in TX length bytes The MCU also signals the transmit logic when the...

Page 30: ...the MCU at the end of the receive operation if the receive data string was shorter than or equal to 8 bytes The MCU receives the interrupt request then checks to determine the reason for the interrup...

Page 31: ...ion If the number of bytes to be transmitted is higher or equal to 5 then the interrupt is generated This occurs also when the number of bytes in the FIFO reaches 3 The MCU should check the IRQ Status...

Page 32: ...tion is when SCLK is high 2 Send address word to IRQ Status register 0x0C with read and continuous address mode bits set to 1 3 Read 1 byte 8 bits from IRQ Status register 0x0C 4 Dummy read 1 byte fro...

Page 33: ...ising edge see Figure 6 17 Communication is terminated when the Slave Select signal goes high All words must be 8 bits long with the MSB transmitted first Figure 6 17 SPI With Slave Select Timing The...

Page 34: ...Low B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 34 TRF7963A SLOS758G DECEMBER 2011 REVISED MARCH 2020 www ti com Submit Documentation Feedback Product Folder Links TRF7963A Detailed Description C...

Page 35: ...ontrol over the RF modulation through the MOD input This mode is provided so that the application can implement a protocol that has the same bit coding as one of the protocols implemented in the reade...

Page 36: ...clock and ASK 10 modulation 0x22 for 6 78 MHz clock and ASK 7 modulation 0x23 for 6 78 MHz clock and ASK 8 5 modulation 0x24 for 6 78 MHz clock and ASK 13 modulation 0x25 for 6 78 MHz clock and ASK 16...

Page 37: ...ver the RF modulation through the MOD input Figure 6 22 Control of RF Modulation Using MOD The microcontroller is responsible for generating data according to the coding specified by the particular st...

Page 38: ...escription Copyright 2011 2020 Texas Instruments Incorporated Figure 6 23 Receive Data Bits and Framing Level ISO IEC 14443 A Step 7 Exit direct mode 0 When an EOF is received data transmission is ove...

Page 39: ...FUNCTION ADDRESS COMMAND B7 Command control bit 0 Address 1 Command 0 1 B6 Read Write 0 Write 1 Read R W 0 B5 Continuous address mode Continuous mode Not used B4 Address Command bit 4 Adr 4 Cmd 4 B3 A...

Page 40: ...er command see Section 6 13 6 The reset mode is automatically terminated at the end of a transmit operation The receiver can stay in reset after end of transmit if the RX Wait Time register 0x08 is se...

Page 41: ...on with tag was performed the command must be preceded by the Enable RX command The Check RF commands require full operation so the receiver must be activated by enable RX or by a normal tag communica...

Page 42: ...ISO14443A High Bit Rate Options R W Section 6 14 1 2 2 0x06 TX Pulse Length Control R W Section 6 14 1 2 3 0x07 RX No Response Wait R W Section 6 14 1 2 4 0x08 RX Wait Time R W Section 6 14 1 2 5 0x0...

Page 43: ...ovides user direct access to AFE direct mode 0 or lets the user add custom framing direct mode 1 Bit 6 of the ISO Control register must be set before entering direct mode 0 or 1 0 ISO mode default Use...

Page 44: ...ID mode 0 RFID mode 1 Reserved should be set to 0 B4 iso_4 RFID See Table 6 18 for B0 B4 settings based on the ISO protocol that the application requires B3 iso_3 RFID B2 iso_2 RFID B1 iso_1 RFID B0 i...

Page 45: ...0 SOF 1 length 02 etu B2 sof_l0 1 SOF 0 length 11 etu 0 SOF 0 length 10 etu B1 l_egt 1 EGT after each byte 0 EGT after last byte is omitted B0 Unused 6 14 1 2 2 ISO14443A High Bit Rate and Parity Opti...

Page 46: ...01 2 36 s for ISO IEC 14443 A at 106 kbps 1 4 s for ISO IEC 14443 A at 212 kbps 737 ns for ISO IEC 14443 A at 424 kbps 442 ns for ISO IEC 14443 A at 848 kbps pulse length control disabled B6 Pul_p1 B5...

Page 47: ...the end of the transmit operation in which the receive decoders are not active held in reset state This prevents incorrect detections resulting from transients following the transmit operation The val...

Page 48: ...of OOK or ASK using the OOK pin is only possible if the function is enabled by setting B6 1 en_ook_p in this register 0x09 and the ISO Control register 0x01 B6 1 When configured this way the MOD pin p...

Page 49: ...FUNCTION DESCRIPTION B7 C212 Band pass 110 kHz to 570 kHz Appropriate for 212 kHz subcarrier system FeliCa B6 C424 Band pass 200 kHz to 900 kHz B5 M848 Band pass 450 kHz to 1 5 MHz Appropriate for Ma...

Page 50: ...K pin becomes modulation output for external TX amplifier B5 io_low 1 Enable low peripheral communication voltage When B5 1 maintains the output driving capabilities of the I O pins connected to the l...

Page 51: ...9 V VDD_A 2 9 V VDD_X 2 9 V 0B 0 0 0 1 VDD_RF 2 8 V VDD_A 2 8 V VDD_X 2 8 V 0B 0 0 0 0 VDD_RF 2 7 V VDD_A 2 7 V VDD_X 2 7 V 1 x don t care Table 6 29 Supply Regulator Setting Automatic 5 V System REG...

Page 52: ...BIT NAME FUNCTION DESCRIPTION B7 Irq_tx IRQ set due to end of TX Signals that TX is in progress The flag is set at the start of TX but the interrupt request IRQ 1 is sent when TX is finished B6 Irg_s...

Page 53: ...rupt enable for FIFO Default 1 B4 En_irq_err1 Interrupt enable for CRC Default 1 B3 En_irq_err2 Interrupt enable for Parity Default 1 B2 En_irq_err3 Interrupt enable for Framing error or EOF Default 1...

Page 54: ...e reader so the new tag response level can be measured Section 6 7 1 1 and Section 6 7 1 2 describe the RSSI levels calculated to RF_IN1 and RF_IN2 The RSSI has 7 steps 3 bits with 4 dB increment The...

Page 55: ...e output selection 0 First stage output used for analog out and digitizing 1 Second stage output used for analog out and digitizing B3 low2 Second stage gain 6 dB HP corner frequency 2 B2 low1 First s...

Page 56: ...B3 Fb3 FIFO bytes fb 3 Bits B0 B3 indicate how many bytes that are loaded in FIFO were not read out yet displays N 1 number of bytes If 8 bytes are in the FIFO this number is 7 also see register 0x0C...

Page 57: ...and EN 0 The register is also automatically reset at TX EOF Table 6 39 TX Length Byte2 Register 0x1E BIT NO BIT NAME FUNCTION DESCRIPTION B7 Txl3 Number of complete byte bn 3 Low nibble of complete i...

Page 58: ...erference The recommended clock frequency on the DATA_CLK line is 2 MHz This schematic shows matching to a 50 port which allows connection to a properly matched 50 antenna circuit or RF measurement eq...

Page 59: ...his Avoid crossing of digital lines under RF signal lines Also avoid crossing of digital lines with other digital lines whenever possible If the crossings are unavoidable 90 crossings should be used t...

Page 60: ...Impedance Matching Smith Chart Resulting power out can be measured with a power meter spectrum analyzer with power meter function or other equipment capable of making a hot measurement Take care to o...

Page 61: ...ully qualified production devices with no prefix Device development evolutionary flow xTRF Experimental device that is not necessarily representative of the electrical specifications of the final devi...

Page 62: ...he entire system current draw over time is of the utmost concern TRF7960A RFID Multiplexer Example System This application report describes the 16 channel high frequency HF 13 56 MHz RFID reader syste...

Page 63: ...metric changes could cause the device not to meet its published specifications 8 8 Export Control Notice Recipient agrees to not knowingly export or re export directly or indirectly any product or tec...

Page 64: ...Texas Instruments Incorporated 9 Mechanical Packaging and Orderable Information The following pages include mechanical packaging and orderable information This information is the most current data av...

Page 65: ...00ppm threshold Antimony trioxide based flame retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard...

Page 66: ...PACKAGE OPTION ADDENDUM www ti com 10 Dec 2020 Addendum Page 2...

Page 67: ...ed to accommodate the component width TAPE DIMENSIONS K0 P1 B0 W A0 Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 User Direction of...

Page 68: ...AND REEL BOX DIMENSIONS Width mm W L H All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TRF7963ARHBR VQFN RHB 32 3000 356 0 356 0 35 0 TRF7963ARHBT...

Page 69: ...IEW Images above are just a representation of the package family actual package may vary Refer to the product data sheet for package details VQFN 1 mm max height RHB 32 PLASTIC QUAD FLATPACK NO LEAD 5...

Page 70: ...2 25 OPTIONAL PIN 1 ID 0 1 C A B 0 05 C EXPOSED THERMAL PAD 33 SYMM SYMM NOTES 1 All linear dimensions are in millimeters Any dimensions in parenthesis are for reference only Dimensioning and toleranc...

Page 71: ...age is designed to be soldered to a thermal pad on the board For more information see Texas Instruments literature number SLUA271 www ti com lit slua271 5 Vias are optional depending on application re...

Page 72: ...4223442 B 08 2019 NOTES continued 6 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release IPC 7525 may have alternate design recommendations 33 SYMM METAL...

Page 73: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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