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SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Detailed Description
Copyright © 2011–2020, Texas Instruments Incorporated
During transmission, the FIFO is checked for an almost-empty condition, and during reception for an
almost-full condition. The maximum number of bytes that can be loaded into the FIFO in a single
sequence is 12 bytes.
NOTE
The number of bytes in a frame, transmitted or received, can be greater than 12 bytes.
During transmission, the MCU loads the TRF7963A FIFO (or, during reception, the MCU removes data
from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile,
the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if
the number of bytes in the FIFO is less than 3 or greater than 9, so that MCU can send new data or
remove the data as necessary. The MCU also checks the number of data bytes to be sent, so as to not
surpass the value defined in TX length bytes. The MCU also signals the transmit logic when the last byte
of data is sent or was removed from the FIFO during reception. Transmission starts automatically after the
first byte is written into FIFO.
Figure 6-10. Checking the FIFO Status Register (Using SPI With SS Mode)
6.12.3 Parallel Interface Mode
In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high.
This is used to reset the interface logic.
, and
show the sequence of
the data, with an 8-bit address word first, followed by data.
Communication is ended by:
•
The StopSmpl condition, where a falling edge on the I/O_7 pin is expected while CLK is high
•
The StopCont condition, where the I/O_7 pin must have a successive rising and falling edge while CLK
is low to reset the parallel interface and be ready for the new communication sequence
•
The StopSmpl condition is also used to terminate the direct mode.