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EMAC Port Registers

5.5

Receive Control Register (RXCONTROL)

The receive control register (RXCONTROL) is shown in

Figure 47

and described in

Table 41

Figure 47. Receive Control Register (RXCONTROL)

Reserved

R-0

Reserved

RXEN

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. Receive Control Register (RXCONTROL) Field Descriptions

Bit

Field

Value

Description

31-1

Reserved

RXEN

Receive DMA enable

Receive is disabled

Receive is enabled

SPRUEF8F – March 2006 – Revised November 2010

C6472/TCI6486 EMAC/MDIO

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Summary of Contents for TMS320C6472

Page 1: ...TMS320C6472 TMS320TCI6486 DSP Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module User s Guide Literature Number SPRUEF8F March 2006 Revised November 2010 ...

Page 3: ... 17 Interrupt Support 67 2 18 Power Management 69 2 19 Emulation Considerations 69 3 EMIC Module Registers 71 3 1 EW_INTCTL Registers 71 3 2 RPIC Registers 71 3 3 TPIC Registers 74 3 4 Prescalar Configuration Register PSCFG 75 4 MDIO Registers 76 4 1 Introduction 76 4 2 MDIO Version Register VERSION 77 4 3 MDIO Control Register CONTROL 78 4 4 PHY Acknowledge Status Register ALIVE 79 4 5 PHY Link S...

Page 4: ...C Interrupt Status Masked Register MACINTSTATMASKED 112 5 19 MAC Interrupt Mask Set Register MACINTMASKSET 113 5 20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR 114 5 21 Receive Multicast Broadcast Promiscuous Channel Enable Register RXMBPENABLE 115 5 22 Receive Unicast Enable Set Register RXUNICASTSET 118 5 23 Receive Unicast Clear Register RXUNICASTCLEAR 119 5 24 Receive Maximum Length Regi...

Page 5: ... 47 Receive Channel 0 7 DMA Head Descriptor Pointer Register RXnHDP 145 5 48 Transmit Channel 0 7 Completion Pointer Register TXnCP 146 5 49 Receive Channel 0 7 Completion Pointer Register RXnCP 147 5 50 Network Statistics Registers 148 Appendix A Glossary 157 Appendix B Revision History 159 5 SPRUEF8F March 2006 Revised November 2010 Contents Submit Documentation Feedback Copyright 2006 2010 Texa...

Page 6: ... 75 29 MDIO Version Register VERSION 77 30 MDIO Control Register CONTROL 78 31 PHY Acknowledge Status Register ALIVE 79 32 PHY Link Status Register LINK 80 33 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW 81 34 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED 82 35 MDIO User Command Complete Interrupt Unmasked Register USERINTRAW 83 36 MDIO User Command Complete Int...

Page 7: ...r Low Priority Frame Threshold Register RXFILTERLOWTHRESH 122 69 Receive Channel n Flow Control Threshold Register RXnFLOWTHRESH 123 70 Receive Channel n Free Buffer Count Register RXnFREEBUFFER 124 71 MAC Control Register MACCONTROL 125 72 MAC Status Register MACSTATUS 127 73 Emulation Control Register EMCONTROL 129 74 FIFO Control Register FIFOCONTROL 130 75 MAC Configuration Register MACCONFIG ...

Page 8: ...ister USERINTRAW Field Descriptions 83 29 MDIO User Command Complete Interrupt Masked Register USERINTMASKED Field Descriptions 84 30 MDIO User Command Complete Interrupt Mask Set Register USERINTMASKSET Field Descriptions 85 31 MDIO User Command Complete Interrupt Mask Clear Register USERINTMASKCLEAR Field Descriptions 86 32 MDIO User Access Register 0 USERACCESS0 Field Descriptions 87 33 MDIO Us...

Page 9: ...5 MAC Control Register MACCONTROL Field Descriptions 125 66 MAC Status Register MACSTATUS Field Descriptions 127 67 Emulation Control Register EMCONTROL Field Descriptions 129 68 FIFO Control Register FIFOCONTROL Field Descriptions 130 69 MAC Configuration Register MACCONFIG Field Descriptions 131 70 Soft Reset Register SOFTRESET Field Descriptions 132 71 MAC Source Address Low Bytes Register MACS...

Page 10: ...elated support tools Copies of these documents are available on the Internet Tip Enter the literature number in the search box provided at www ti com SPRU189 TMS320C6000 DSP CPU and Instruction Set Reference Guide Describes the CPU architecture pipeline instruction set and interrupts for the TMS320C6000 digital signal processors DSPs SPRU198 TMS320C6000 Programmer s Guide Describes ways to optimiz...

Page 11: ...port three types of interfaces to the physical layer device PHY reduced pin count media independent interface RMII reduced pin count gigabit media independent interface RGMII and source synchronous serial independent interface S3MII In addition to above four EMAC0 natively supports an additional two interfaces standard media independent interface MII and standard gigabit media independent interfac...

Page 12: ...1 Module Introduction www ti com Single MDIO shared by both EMAC modules 1 3 Functional Block Diagram Figure 1 shows the functional block diagram of the EMAC peripherals used in the TCI6486 C6472 device It consists mainly of EMAC0 EMAC1 CPPI buffer manager per EMAC EMIC per EMAC MDIO Figure 1 EMAC and MDIO Block Diagram 12 C6472 TCI6486 EMAC MDIO SPRUEF8F March 2006 Revised November 2010 Submit Do...

Page 13: ...h two signals MDCLK output clock and MDIO bi directional data For details of MDIO operation and signals see Section 2 8 The device has two serial management interfaces although only one is used based on the interface selection of EMAC0 Table 1 shows the two sets of pins associated with serial management interface One serial management interface is for RGMII needed at 1 8 V HSTL buffer and the othe...

Page 14: ...liance Statement The EMAC peripheral conforms to the IEEE 802 3 standard describing the Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer specifications ISO IEC has also adopted the IEEE 802 3 standard and re designated it as ISO IEC 8802 3 2000 E In difference from this standard the EMAC peripheral integrated with the TCI6486 C6472 device does not use...

Page 15: ... 1 MII Clocking The MII interface is supported by EMAC0 only When MACSEL0 is set to zero 000b the transmit and receive clock sources are provided from an external PHY via the MTCLK and MRCLK pins These clocks are inputs to the EMAC module and operate at 2 5 MHz in 10 Mbps mode and at 25 MHz in 100 MHz mode The MII clocking interface is not used in 1000 Mbps mode For timing purposes data is transmi...

Page 16: ...duced pinout The RGMII protocol also allows for dynamic switching of the mode between 10 100 1000 Mbps modes This negotiation data is embedded in the incoming data stream from the external PHY For timing purposes data is transmitted and received with respect to MTCLK and MRCLK respectively The RGMII interface has separate I O pins from the other EMAC pins because the interface voltage is different...

Page 17: ... 10 RGMII 11 RMII Table 6 explains the decoding of MACSEL0 2 0 MACSEL1 1 0 and EMAC1_EN of the DEVCTL register Table 6 MACSEL0 2 0 MACSEL1 1 0 and EMAC1_EN Decoding MACSEL02 MACSEL01 MACSEL00 MACSEL11 MACSEL10 EMAC_EN EMAC0 EMAC1 0 0 0 X X 0 MII None 0 0 0 0 X 1 MII None 0 0 0 1 0 1 MII RGMII 0 1 0 X X 0 GMII None 0 1 0 0 X 1 GMII None 0 1 0 1 0 1 GMII RGMII 0 0 1 X X 0 RMII None 0 1 1 X X 0 RGMII...

Page 18: ...II 2 3 1 Media Independent Interface MII Connections Figure 2 shows a TCI6486 C6472 device with integrated EMAC and MDIO interfaced to the PHY via an MII connection This interface is only available in 10 Mbps and 100 Mbps modes Figure 2 Ethernet Configuration with MII Interface Table 7 summarizes the individual EMAC and MDIO signals for the MII interface For more information refer to either the IE...

Page 19: ...3 0 I Receive data MRXD The receive data pins are a collection of 4 data signals comprising 4 bits of data MRDX0 is the least significant bit LSB The signals are synchronized by MRCLK and valid only when MRXDV is asserted MRXDV I Receive data valid MRXDV The receive data valid signal indicates that the MRXD pins are generating nibble data for use by the EMAC It is driven synchronously to MRCLK MRX...

Page 20: ...ion RMTXD 1 0 O Transmit data RMTXD The transmit data pins are a collection of 2 data signals comprising 2 bits of data RMTDX0 is the least significant bit LSB The signals are synchronized to the RMII reference clock and valid only when RMTXEN is asserted RMTXEN O Transmit enable RMTXEN The transmit enable signal indicates that the RMTXD pins are generating nibble data for use by the PHY It is dri...

Page 21: ...elay clock buffer If multiple RMII PHY ports are used all device RMII reference clocks must come from same zero delay clock buffer On the TCI6486 C6472 device RMII pins are multiplexed with other non RGMII pins When using the RMII0 port on EMAC0 there are no restrictions on the available EMAC1 Ethernet interfaces RMII1 S3MII1 and RGMII1 are useable When using the RMII1 port on EMAC1 the EMAC0 Ethe...

Page 22: ...5 MHz at 10 Mbps operation 25 MHz at 100 Mbps operation and 125 MHz at 1000 Mbps operation MRXD 7 0 I Receive data MRXD The receive data pins are a collection of 8 data signals comprising 8 bits of data MRDX0 is the least significant bit LSB The signals are synchronized by MRCLK and valid only when MRXDV is asserted MRXDV I Receive data valid MRXDV The receive data valid signal indicates that the ...

Page 23: ... comprising 4 bits of data RGTDX0 is the least significant bit LSB The signals are synchronized by RGTXC and valid only when RGTXCTL is asserted The lower 4 bits of data are transmitted on the rising edge of the clock and the higher 4 bits of data are transmitted on the falling edge of the RGTXC RGTXCTL O Transmit enable RGTXCTL The transmit enable signal indicates that the RGTXD pins are generati...

Page 24: ...the falling edge of RGRXC RGMDCLK O Management data clock RGMDCLK The RGMDIO data clock is sourced by the MDIO module It synchronizes MDIO data access operations done on the RGMDIO pin The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register CONTROL RGMDIO I O Management data input output RGMDIO The RGMDIO pin drives PHY management data into and out of the PHY by w...

Page 25: ...3MII Connections Figure 6 shows a TCI6486 C6472 device with an integrated EMAC and MDIO interface via S3MII connections connected to a PHY The S3MII interface supports source synchronous 10 Mbps and 100 Mbps operations with full and half duplex support Figure 6 Ethernet Configuration with S3MII Interface 25 SPRUEF8F March 2006 Revised November 2010 C6472 TCI6486 EMAC MDIO Submit Documentation Feed...

Page 26: ...DIO data access operations done on the MDIO pin The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register CONTROL MDIO I O Management data input output MDIO The MDIO pin drives PHY management data into and out of the PHY via an access frame consisting of start of frame read write indication PHY address register address and data bit cycles The MDIO pin acts as an out...

Page 27: ...ck buffer 125 MHz XO Low skew buffer Zero delay clock buffer External logic element S3MII multi PHY TX_CLK TX_SYNC P0_TXD P0_RXD P1_TXD P1_RXD Pn_TXD Pn_RXD RX_SYNC RX_CLK www ti com EMAC Functional Architecture Figure 7 S3MII Multi PHY Configuration 27 SPRUEF8F March 2006 Revised November 2010 C6472 TCI6486 EMAC MDIO Submit Documentation Feedback Copyright 2006 2010 Texas Instruments Incorporated...

Page 28: ... the case of the S3MII switch where the switch has only one TX_SYNC for all ports external logic is needed to synchronize the TX_SYNC signals from multiple ports or TCI6486 C6472 devices The TXD signal from the multiple ports should also be synchronized using external logic since the clock phase relation of different TCI6486 C6472 devices can be different Figure 8 demonstrates the example mutli PH...

Page 29: ...t may be an individual or multicast including broadcast address If the destination EMAC port receives an Ethernet frame with a destination address that does not match any of its MAC physical addresses and no promiscuous multicast or broadcast channel is enabled it discards the frame Source 6 This field contains the MAC address of the Ethernet port that transmits the frame to the address Local Area...

Page 30: ...ansmit the frame If the port senses that the transmission medium is busy it waits until it senses no signal energy plus an inter packet gap time and then starts to transmit the frame 3 While transmitting the port monitors for the presence of signal energy coming from other ports If the port transmits the entire frame without detecting signal energy from other ethernet devices the port is finished ...

Page 31: ...ist 1 Buffer Pointer The buffer pointer refers to the memory buffer that either contains packet data during transmit operations or is an empty buffer ready to receive packet data during receive operations 2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data This field only has meaning when the buffer descriptor points to a buffer that ...

Page 32: ...registers for both They are designated as follows TXnHDP Transmit Channel n DMA Head Descriptor Pointer Register RXnHDP Receive Channel n DMA Head Descriptor Pointer Register After an EMAC reset and before enabling the EMAC for send or receive you must initialize all 16 head descriptor pointer registers to zero The EMAC uses a simple system to determine ownership of a descriptor either the EMAC or...

Page 33: ...he linked list queue mechanism Section 2 5 2 The EMAC synchronizes the descriptor list processing by using interrupts to the software application The interrupts are controlled by the application by using the interrupt masks global interrupt enable and the completion pointer register CP This register is also called interrupt acknowledge register As the EMAC supports eight channels for both transmit...

Page 34: ...h Example 1 Transmit Descriptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next descriptor in chain Uint8 pBuffer Pointer to data buffer Uint32 BufOffLen Buffer Offset MSW and Length LSW Uint32 PktFlgLen Packet Flags MSW and Length LSW EMAC_Desc Packet Flags define EMAC_DSC...

Page 35: ...uffer data starts on byte 16 of the buffer The software application must set this value prior to adding the descriptor to the active transmit list This field is not altered by the EMAC Note that this value is only checked on the first descriptor of a given packet where the SOP flag is set It cannot specify the offset of subsequent packet fragments Also as the buffer pointer may point to any byte a...

Page 36: ...cation can use this bit to detect when the EMAC transmitter for the corresponding channel has halted This is useful when the application appends additional packet descriptors to a transmit queue list that is already owned by the EMAC Note that this flag is valid on EOP descriptors only 2 5 4 10 Teardown Complete TDOWNCMPLT Flag This flag is used when a transmit queue is being torn down or aborted ...

Page 37: ...c struct _EMAC_Desc pNext Pointer to next descriptor in chain Uint8 pBuffer Pointer to data buffer Uint32 BufOffLen Buffer Offset MSW and Length LSW Uint32 PktFlgLen Packet Flags MSW and Length LSW EMAC_Desc Packet Flags define EMAC_DSC_FLAG_SOP 0x80000000u define EMAC_DSC_FLAG_EOP 0x40000000u define EMAC_DSC_FLAG_OWNER 0x20000000u define EMAC_DSC_FLAG_EOQ 0x10000000u define EMAC_DSC_FLAG_TDOWNCMP...

Page 38: ...value of the register and this value is also written to the buffer offset field of the descriptor When a packet is fragmented over multiple buffers because it does not fit in the first buffer supplied the buffer offset only applies to the first buffer in the list which is where the start of packet SOP flag is set in the corresponding buffer descriptor In other words the buffer offset field is only...

Page 39: ...eive list the next descriptor pointer is NULL The software application uses this bit to detect when the EMAC receiver for the corresponding channel has halted This is useful when the application appends additional free buffer descriptors to an active receive queue Note that this flag is valid on EOP descriptors only 2 5 5 10 Teardown Complete TDOWNCMPLT Flag This flag is used when a receive queue ...

Page 40: ...efers to the data structures used by the EMAC to describe transmit and receive packets and the application programming interface to manipulate the data structures The CPPI maximizes the efficiency of communication between host processor and EMAC It minimizes the host interaction maximizes the memory use efficiency and maximizes the symmetry between transmit and receive operations Some of the impor...

Page 41: ...ombiner MACTXINT4 RX pacer and interrupt combiner MACRXINT4 Common interrupt combiner MACINT4 TX pacer and interrupt combiner MACTXINT5 RX pacer and interrupt combiner MACRXINT5 Common interrupt combiner MACINT5 Registers Prescaler PS_TICK EMAC interrupts 18 MDIO interrupts 2 Peripheral bus reset Peripheral bus clock To GEM0 To GEM1 To GEM2 To GEM3 To GEM5 To GEM4 Peripheral bus www ti com EMAC Fu...

Page 42: ... every single interrupt This block provides time based or count based pacing of interrupts in any combination In addition this block supports reprogramming of timer value and count value without hardware software race condition and also facilitates use of the same timer and count values for the next event period The EVT_IN is the pulse interrupt from EMAC This is forwarded to timed delay and divid...

Page 43: ... TIME_CFG is set to a non zero value an output pulse is generated after the TIME_CFG number of prescalar output periods The counter starts counting on the first event The state machine has three states WAITING DELAY and OUTPUT Upon reset the state machine is placed in the WAITING state The state machine makes transitions between the states as shown in Figure 16 Note that states that are grayed out...

Page 44: ...ay when the TIME_CFG is also set to 0 i e timed delay SM is disabled When the TIME_CFG is set to non zero it then disables the divide by N state machine When the CNT_CFG is set to non zero the CNT_CFG number of events are counted before an output pulse is generated The counter resets and reloads every time when a divide by N pulse is generated The state machine has three states WAITING COUNT and O...

Page 45: ... Optionally implements pacing for transmit events Combines the output of the pacer module based on the settings of the bits 8 to 15 in the EW_INTCTL register and generates a single MACTXINT interrupt per the C64x megamodule Receives a single PS_TICK and forwards it to all the pacing blocks Allows per interrupt enabling or disabling of the interrupts the setting of bits 8 to 15 in the EW_INTCTL reg...

Page 46: ...ms following functions Implements pacing for receive events Combines the output of the pacer module based on the settings of bits 16 to 23 in the EW_INTCTL register and generates a single MACRXINT interrupt per the C64x megamodule Receives a single PS_TICK and forwards it to all the pacing blocks Allows per interrupt enabling or disabling of the interrupts the setting of bits 16 to 23 in the EW_IN...

Page 47: ...tion of the MDIO interface with little maintenance from the CPU The MDIO module enumerates all PHY devices in the system by continuously polling 32 MDIO addresses Once it detects a PHY device the MDIO module reads the PHY status register to monitor the PHY link state The MDIO module stores link change events that can interrupt the CPU The event storage allows the CPU to poll the link status of the...

Page 48: ...stem is using more than one PHY The software application can then quickly switch between PHYs based on their current link status 2 8 1 3 Active PHY Monitoring Once a PHY candidate has been selected for use the MDIO module transparently monitors its link state by reading the PHY status register The MDIO device stores link change events that may optionally interrupt the CPU Thus the system can poll ...

Page 49: ...nitored PHYs sets the appropriate bit in the LINKINTRAW and LINKINTMASKED registers if they are enabled by the LINKINTENB bit in USERPHYSELn While the MDIO module is enabled the host can issue a read or write transaction over the management interface using the DATA PHYADR REGADR and WRITE bits in the USERACCESSn register When the application sets the GO bit in USERACCESSn the MDIO module begins th...

Page 50: ... after the module completes the read operation on the serial bus Completion of the read operation can be determined by polling the GO and ACK bits in USERACCESSn Once the GO bit has cleared the ACK bit is set on a successful read 4 Completion of the operation sets the corresponding bit in the USERINTRAW register for the USERACCESSn used If interrupts have been enabled on this bit using the USERINT...

Page 51: ...ally checking the PHY state in the ALIVE register Example 3 MDIO Register Access Macros define PHYREG_read regadr phyadr MDIO_REGS USERACCESS0 CSL_FMK MDIO_USERACCESS0_GO 1u CSL_FMK MDIO_USERACCESS0_REGADR regadr CSL_FMK MDIO_USERACCESS0_PHYADR phyadr define PHYREG_write regadr phyadr data MDIO_REGS USERACCESS0 CSL_FMK MDIO_USERACCESS0_GO 1u CSL_FMK MDIO_USERACCESS0_WRITE 1 CSL_FMK MDIO_USERACCESS...

Page 52: ... CPPI buffer manager This DMA engine is totally independent of the TCI6486 C6472 DSP EDMA Receive FIFO The receive FIFO consists of 68 cells of 64 bytes each and the associated control logic The FIFO buffers receive data in preparation for writing into packet buffers in device memory and also enable receive FIFO flow control MAC receiver The MAC receiver detects and processes incoming network fram...

Page 53: ...itiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM block The transmit DMA controller then fetches the first packet in the packet chain from memory The DMA controller writes the packet into the transmit FIFO in bursts of 64 byte cells The MAC transmitter initiates the packet transmission when either the threshold number of cells configurabl...

Page 54: ...wing sections discuss the operation of these interfaces in 10 100 Mbps mode MII RMII GMII and RGMII and 1000 Mbps mode GMII and RGMII An IEEE 802 3 compliant Ethernet MAC controls these interfaces 2 10 1 Data Reception 2 10 1 1 Receive Control Data received from the PHY is interpreted and output to the EMAC receive FIFO Interpretation involves detection and removal of the preamble and start of fra...

Page 55: ...ue of the incoming frame destination address A collision is generated for any incoming packet regardless of the destination address if any EMAC enabled channel s free buffer register value is less than or equal to the channel s flow threshold value 2 10 1 5 IEEE 802 3X Based Receive Buffer Flow Control IEEE 802 3x based receive buffer flow control provides a means of preventing frame reception whe...

Page 56: ...0 2 3 Adaptive Performance Optimization APO The EMAC incorporates adaptive performance optimization APO logic that may be enabled by setting the TXPACE bit in the MACCONTROL register Transmission pacing to enhance performance is enabled when the TXPACE bit is set Adaptive performance pacing introduces delays into the normal transmission of frames delaying transmission attempts between stations and...

Page 57: ... or the new pause time value is 0 and the transmit pause timer immediately expires Otherwise the EMAC transmit pause timer is set immediately to the new pause frame pause time value Any remaining pause time from the previous pause frame is discarded If the TXFLOWEN bit in MACCONTROL is cleared then the pause timer immediately expires The EMAC does not start the transmission of a new data frame any...

Page 58: ...ingle channel selected by the RXBROADCH field of RXMBPENABLE register The RXMULTEN bit in the RXMBPENABLE register determines if hash matching multicast frames are enabled or filtered Incoming multicast addresses group addresses are hashed into an index in the hash table If the indexed bit is set the frame hash will match and it will be transferred to the channel selected by the RXMULTCH field whe...

Page 59: ...h type field value not equal to 81 00h are low priority frames Received frames that contain priority information are determined by the EMAC as A 48 bit 6 bytes destination address equal to The destination station s individual unicast address The destination station s multicast address MACHASH1 and MACHASH2 registers The broadcast address of all ones A 48 byte 6 bytes source address The 16 bit 2 by...

Page 60: ...XLEN register default reset value is 5EEh 1518 in decimal Long received frames are either oversized or jabber frames Long frames with no errors are oversized frames long frames with CRC code or alignment errors are jabber frames Received frames are short frames if their frame count is less than 64 bytes Short frames that address match and contain no errors are undersized frames short frames with C...

Page 61: ...dress RXMBPENABLE Bits Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame Treatment 0 0 X X X No frames transferred 0 1 0 0 0 Proper frames transferred to promiscuous channel 0 1 0 0 1 Proper undersized data frames transferred to promiscuous channel 0 1 0 1 0 Proper data and control frames transferred to promiscuous channel 0 1 0 1 1 Proper undersized data and control frames transferred to promiscuous ch...

Page 62: ...andled for the middle of frame overrun Table 15 Middle of Frame Overrun Treatment Address Match RXCAFEN RXCEFEN Middle of Frame Overrun Treatment 0 0 X Overrun frame filtered 0 1 0 Overrun frame filtered 0 1 1 As much frame data as possible is transferred to the promiscuous channel until overrun The appropriate overrun statistic s is incremented and the OVERRUN and NOMATCH flags are set in the SOP...

Page 63: ...HRESH cells configurable through the FIFOCONTROL register or a complete packet are available in the FIFO Transmit underrun cannot occur for packet sizes of TXCELLTHRESH times 64 bytes or less For larger packet sizes transmit underrun can occur if the memory latency is greater than the time required to transmit a 64 byte cell on the wire this is 0 512 ms in 1 Gbit mode 5 12 ms in 100 Mbps mode and ...

Page 64: ...IO EMIC modules and CPPI buffer managers cannot be placed in reset from a register inside their memory map 2 15 2 Hardware Reset Considerations When a hardware reset occurs the EMAC peripheral will have its register values reset and all the sub modules will return to their default state After the hardware reset the EMAC needs to be initialized before resuming its data transmission as described in ...

Page 65: ... EMAC and MDIO modules Enabling interrupts in the EW_INTCTL Use the system s interrupt controller to map the EMAC interrupts to one of the CPU s interrupts Once the interrupt is mapped to a CPU interrupt general masking and unmasking of the interrupt to control reentrancy should be done at the chip level by manipulating the interrupt enable mask The EMIC module interrupt control register EW_INTCTL...

Page 66: ...gisters 6 Initialize the RXnFREEBUFFER RXnFLOWTHRESH and RXFILTERLOWTHRESH registers if buffer flow control is to be enabled Program the FIFOCONTROL register if FIFO flow control is desired 7 Most device drivers open with no multicast addresses so clear the MACHASH1 and MACHASH2 registers 8 Write the RXBUFFEROFFSET register value typically zero 9 Initially clear all unicast channels by writing FFh...

Page 67: ...en by the EMAC port address of last buffer descriptor used by the EMAC If the two values are not equal indicating that the EMAC has transmitted more packets than the CPU has processed interrupts for then the transmit packet completion interrupt signal remains asserted If the two values are equal indicating that the host has processed all packets that the EMAC has transferred then the pending inter...

Page 68: ... 0000h if it has been enabled by the STATMASK bit in the MACINTMASKSET register The statistics interrupt is removed by writing to decrement any statistics value greater than 8000 0000h The interrupt remains asserted as long as the most significant bit of any statistics value is set 2 17 1 4 Host Error Interrupt The host error interrupt HOSTPEND is issued if enabled under error conditions due to th...

Page 69: ...MIC module For safe interrupt processing the software application should disable interrupts using the EMIC module interrupt control register EW_INTCTL upon entry to the ISR and re enable them upon leaving the ISR 2 17 4 Interrupt Multiplexing The EMIC module combines different interrupt signals from both the EMAC and MDIO modules and generates a single interrupt signal that is wired to the CPU int...

Page 70: ...it cell FIFO will be transmitted For receive frames that are detected by the EMAC after the suspend state is entered are ignored No statistics will be kept for ignored frames Table 16 shows how the SOFT and FREE bits affect the operation of the emulation suspend Table 16 Emulation Control SOFT FREE Description 0 0 Normal operation 1 0 Emulation suspend X 1 Normal operation 70 C6472 TCI6486 EMAC MD...

Page 71: ...interrupts in the transmit group is asserted by EMAC Generation of MACRXINTX is conditional on the following At least one of the pulse interrupts in the receive group is enabled At least one of the enabled pulse interrupts in the receive group is asserted by EMAC Figure 23 EW_INTCTL Register 31 24 Reserved 0000 0000 23 22 21 20 19 18 17 16 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 R W 0 R W 0 R W 0 R W 0 R ...

Page 72: ...ed 27 16 TIME_CFG Time delay configuration value 15 8 CNT_CFG Divide by N configuration value 7 4 Reserved Reserved 3 TU Write only bit reads return 0 0 N A 1 Enables writes to TIME_CFG 2 CU Write only bit reads return 0 0 N A 1 Enables writes to CNT_CFG 1 TR Write only bit reads return 0 0 N A 1 Resets the timer counter 0 CR Write only bit reads return 0 0 N A 1 Resets the divide by N count 72 C6...

Page 73: ... only n value after reset Table 18 RPSTAT Register Field Descriptions Bit Field Value Description 31 28 Reserved Reserved 27 16 TIME Current time delay value 15 8 CNT Current divide by N value 7 4 Reserved Reserved 3 2 TIM_SM Time delay SM 00 Time delay SM in WAITING state 01 Time delay SM in DELAY state 10 Time delay SM in OUTPUT state 11 Reserved 1 0 DIV_SM Divide by N SM 00 Divide by N SM in WA...

Page 74: ...ite R Read only n value after reset Table 19 TPCFG Register Field Descriptions Bit Field Value Description 31 28 Reserved Reserved 27 16 TIME_CFG Time delay configuration value 15 8 CNT_CFG Divide by N configuration value 7 4 Reserved Reserved 3 TU Write only bit reads return 0 0 N A 1 Enables writes to TIME_CFG 2 CU Write only bit reads return 0 0 N A 1 Enables writes to CNT_CFG 1 TR Write only b...

Page 75: ...vide by N value 7 4 Reserved Reserved 3 2 TIM_SM Time delay SM 00 Time delay SM in WAITING state 01 Time delay SM in DELAY state 10 Time delay SM in OUTPUT state 11 Reserved 1 0 DIV_SM Divide by N SM 00 Divide by N SM in WAITING state 01 Divide by N SM in DELAY state 10 Divide by N SM in OUTPUT state 11 Reserved 3 4 Prescalar Configuration Register PSCFG There is a single PSCFG register for the wr...

Page 76: ...Status Change Interrupt Unmasked Register Section 4 6 14h LINKINTMASKED MDIO Link Status Change Interrupt Masked Register Section 4 7 20h USERINTRAW MDIO User Command Complete Interrupt Unmasked Section 4 8 Register 24h USERINTMASKED MDIO User Command Complete Interrupt Masked Register Section 4 9 28h USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register Section 4 10 2Ch USERINTMAS...

Page 77: ... only R W Read Write n value after reset Table 22 MDIO Version Register VERSION Field Descriptions Bit Field Value Description 31 16 MODID Identifies the type of peripheral 15 8 REVMAJ Management Interface Module major revision value 7 0 REVMIN Management Interface Module minor revision value 77 SPRUEF8F March 2006 Revised November 2010 C6472 TCI6486 EMAC MDIO Submit Documentation Feedback Copyrig...

Page 78: ... the module It is currently set to 1 This implies that MDIOUserAccess1 is the highest available user access channel 23 21 Reserved 0 Reserved 20 PREAMBLE Preamble disable 0 Standard MDIO preamble is used 1 Disables this device from sending MDIO frame preambles 19 FAULT Fault indicator This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them This indicates a phys...

Page 79: ... corresponding to the register bit number was acknowledged by the PHY the bit is reset if the PHY fails to acknowledge the access Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated The alive bits are only meant to be used to give an indication of the presence or not of a PHY with the corresponding address Writing a 1 to any bit will clear it writing a ...

Page 80: ...c Status Register of a PHY The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction The bit is reset if the PHY indicates it does not have a link or fails to acknowledge the read transaction Writes to the register have no effect 0 The PHY indicates it does not have a link or fails to acknowledge the read transaction 1 The PHY with the correspo...

Page 81: ...tatus Change Interrupt Unmasked Register LINKINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 LINKINTRAW MDIO Link change event raw value When asserted a bit indicates that there was an MDIO link change event a change in the LINK register corresponding to the PHY address in the USERPHYSEL register LINKINTRAW 0 and LINKINTRAW 1 correspond to USERPHYSEL0 and USERPHY...

Page 82: ...asked Register LINKINTMASKED Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 LINKINTMASKED MDIO Link change interrupt masked value hen asserted a bit indicates that there was an MDIO link change event a change in the LINK register corresponding to the PHY address in the USERPHYSEL register and the corresponding LINKINTENB bit was set LINKINTRAW 0 and LINKINTRAW 1 corres...

Page 83: ... 1 to clear n value after reset Table 28 MDIO User Command Complete Interrupt Unmasked Register USERINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTRAW MDIO User command complete event bits When asserted a bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS register has completed Writing a 1 will clear the...

Page 84: ...ble 29 MDIO User Command Complete Interrupt Masked Register USERINTMASKED Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKED Masked value of MDIO User command complete interrupt When asserted a bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS register has completed and the corresponding USERINTMASKSET bit ...

Page 85: ...Table 30 MDIO User Command Complete Interrupt Mask Set Register USERINTMASKSET Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKSET MDIO user interrupt mask set for USERINTMASKED 1 0 respectively Setting a bit to 1 will enable MDIO user command complete interrupts for that particular USERACCESS register MDIO user interrupt for a particular USERACCESS register ...

Page 86: ...Read Write 1 to clear n value after reset Table 31 MDIO User Command Complete Interrupt Mask Clear Register USERINTMASKCLEAR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKCLEAR MDIO user command complete interrupt mask clear for USERINTMASKED 1 0 respectively Setting a bit to 1 will disable further user command complete interrupts for that particular USERAC...

Page 87: ... machine is enabled This bit will self clear when the requested access has been completed Any writes to the USERACCESS0 register are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to a 1 causes the MDIO transaction to be a register write otherwise it is a register read 0 The user command is a read operation 1 The user command is a write operation 29 ACK Acknowledge bit Thi...

Page 88: ... status determination select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for PHY address specified in PHYADRMON Link change interrupts are disabled if this bit is set to 0 0 Link change interrupts are disab...

Page 89: ...e machine is enabled This bit will self clear when the requested access has been completed Any writes to the USERACCESS0 register are blocked when the go bit is 1 30 WRITE Write enable bit Setting this bit to a 1 causes the MDIO transaction to be a register write otherwise it is a register read 0 The user command is a read operation 1 The user command is a write operation 29 ACK Acknowledge bit Th...

Page 90: ... status determination select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for PHY address specified in PHYADRMON Link change interrupts are disabled if this bit is set to 0 0 Link change interrupts are disab...

Page 91: ...gister Section 5 19 BCh MACINTMASKCLEAR MAC Interrupt Mask Clear Register Section 5 20 100h RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Section 5 21 Register 104h RXUNICASTSET Receive Unicast Enable Set Register Section 5 22 108h RXUNICASTCLEAR Receive Unicast Clear Register Section 5 23 10Ch RXMAXLEN Receive Maximum Length Register Section 5 24 110h RXBUFFEROFFSET Receive B...

Page 92: ...h TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register Section 5 46 614h TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register Section 5 46 618h TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register Section 5 46 61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 5 46 620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 5 47...

Page 93: ...l number of undersized frames received Section 5 50 9 224h RXFRAGMENTS Receive Frame Fragments Register Section 5 50 10 228h RXFILTERED Filtered Receive Frames Section 5 50 11 22Ch RXQOSFILTERED Received Frames Filtered by QOS Section 5 50 12 230h RXOCTETS Total number of received bytes in good frames Section 5 50 13 234h TXGOODFRAMES Total number of good frames transmitted Section 5 50 14 238h TX...

Page 94: ...t Frames Register Section 5 50 33 284h RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register Section 5 50 34 288h RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register Section 5 50 35 28Ch RXDMAOVERRUNS Receive DMA Start of Frame and Middle of Frame Overruns Section 5 50 36 Register 94 C6472 TCI6486 EMAC MDIO SPRUEF8F March 2006 Revised November 2010 Submit Documentation...

Page 95: ... TXMAJORVER TXMINORVER 0x01 0x02 0x08 LEGEND R Read only n value after reset Table 37 Transmit Identification and Version Register TXIDVER Field Descriptions Bit Field Value Description 31 16 TXIDENT Transmit identification value 15 11 RTLVER RTL version value 10 8 TXMAJORVER Transmit major version value 7 0 TXMINORVER Transmit minor version value 95 SPRUEF8F March 2006 Revised November 2010 C6472...

Page 96: ... 0 15 1 0 Reserved TXEN R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 38 Transmit Control Register TXCONTROL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 TXEN Transmit enable 0 Transmit is disabled 1 Transmit is enabled 96 C6472 TCI6486 EMAC MDIO SPRUEF8F March 2006 Revised November 2010 Submit Documentation Feedback Copyright 2006 2010 Texas In...

Page 97: ...dy Read as zero but is always assumed to be one unused 30 3 Reserved 0 Reserved 2 0 TXTDNCH Transmit teardown channel The transmit teardown channel is commanded by writing the encoded value of the transmit channel to be torn down The teardown register is read as zero 0 Teardown transmit channel 0 1h Teardown transmit channel 1 2h Teardown transmit channel 2 3h Teardown transmit channel 3 4h Teardo...

Page 98: ...R RXMAJORVER RXMINORVER 0x01 0x02 0x08 LEGEND R Read only n value after reset Table 40 Receive Identification and Version Register RXIDVER Field Descriptions Bit Field Value Description 31 16 RXIDENT Receive identification value 15 11 RTLVER RTL version value 10 8 RXMAJORVER Receive major version value 7 0 RXMINORVER Receive minor version value 98 C6472 TCI6486 EMAC MDIO SPRUEF8F March 2006 Revise...

Page 99: ...0 15 1 0 Reserved RXEN R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 41 Receive Control Register RXCONTROL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 RXEN Receive DMA enable 0 Receive is disabled 1 Receive is enabled 99 SPRUEF8F March 2006 Revised November 2010 C6472 TCI6486 EMAC MDIO Submit Documentation Feedback Copyright 2006 2010 Texas Ins...

Page 100: ...ready Read as zero but is always assumed to be one unused 30 3 Reserved 0 Reserved 2 0 RXTDNCH Receive teardown channel Receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down The teardown register is read as zero 0 Teardown receive channel 0 1h Teardown receive channel 1 2h Teardown receive channel 2 3h Teardown receive channel 3 4h Teardown recei...

Page 101: ...3 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND TX7PEND raw interrupt read before mask 6 TX6PEND TX6PEND raw interrupt read before mask 5 TX5PEND TX5PEND raw interrupt read before mask 4 TX4PEND TX4PEND raw interrupt read before mask 3 TX3PEND TX3PEND raw interrupt read before mask 2 TX2PEND TX2PEND raw in...

Page 102: ...R Read only n value after reset Table 44 Transmit Interrupt Status Masked Register TXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND TX7PEND masked interrupt read 6 TX6PEND TX6PEND masked interrupt read 5 TX5PEND TX5PEND masked interrupt read 4 TX4PEND TX4PEND masked interrupt read 3 TX3PEND TX3PEND masked interrupt read 2 TX2PEND TX2PEND masked inte...

Page 103: ...ask Write 1 to enable interrupt 19 TX3PULSEMASK 0 Transmit channel 3 pulse interrupt mask Write 1 to enable interrupt 18 TX2PULSEMASK 0 Transmit channel 2 pulse interrupt mask Write 1 to enable interrupt 17 TX1PULSEMASK 0 Transmit channel 1 pulse interrupt mask Write 1 to enable interrupt 16 TX0PULSEMASK 0 Transmit channel 0 pulse interrupt mask Write 1 to enable interrupt 15 8 Reserved 0 Reserved...

Page 104: ...pt mask Write 1 to disable interrupt 19 TX3PULSEMASK 0 Transmit channel 3 pulse interrupt mask Write 1 to disable interrupt 18 TX2PULSEMASK 0 Transmit channel 2 pulse interrupt mask Write 1 to disable interrupt 17 TX1PULSEMASK 0 Transmit channel 1 pulse interrupt mask Write 1 to disable interrupt 16 TX0PULSEMASK 0 Transmit channel 0 pulse interrupt mask Write 1 to disable interrupt 15 8 Reserved 0...

Page 105: ...ion 31 USERINT MDIO module user interrupt USERINT pending status bit 30 LINKINT MDIO module link change interrupt LINKINT pending status bit 29 18 Reserved 0 Reserved 17 HOSTPEND EMAC module host error interrupt HOSTPEND pending status bit 16 STATPEND EMAC module statistics interrupt STATPEND pending status bit 15 8 RXPEND Receive channels 0 7 interrupt RXnPEND pending status bit Bit 8 is receive ...

Page 106: ... Vector Register MACEOIVECTOR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 MAC_EOI_VECTOR MAC end of interrupt vector The EOI_VECTOR 4 0 pins reflect the value written to this location one peripheral bus clock cycle after a write to this location The EOI_WR signal is asserted for a single clock cycle after a latency of two peripheral bus clock cycles when a write is pe...

Page 107: ... Receive Interrupt Status Unmasked Register RXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 RX7PEND RX7PEND raw interrupt read before mask 6 RX6PEND RX6PEND raw interrupt read before mask 5 RX5PEND RX5PEND raw interrupt read before mask 4 RX4PEND RX4PEND raw interrupt read before mask 3 RX3PEND RX3PEND raw interrupt read before mask 2 RX2PEND RX2PEND raw inte...

Page 108: ...ead only n value after reset Table 50 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 RX7PEND RX7PEND masked interrupt read 6 RX6PEND RX6PEND masked interrupt read 5 RX5PEND RX5PEND masked interrupt read 4 RX4PEND RX4PEND masked interrupt read 3 RX3PEND RX3PEND masked interrupt read 2 RX2PEND RX2PEND masked interrup...

Page 109: ...t mask Write 1 to enable interrupt 19 RX3PULSEMASK 0 Receive channel 3 pulse interrupt mask Write 1 to enable interrupt 18 RX2PULSEMASK 0 Receive channel 2 pulse interrupt mask Write 1 to enable interrupt 17 RX1PULSEMASK 0 Receive channel 1 pulse interrupt mask Write 1 to enable interrupt 16 RX0PULSEMASK 0 Receive channel 0 pulse interrupt mask Write 1 to enable interrupt 15 8 Reserved 0 Reserved ...

Page 110: ...4 pulse interrupt mask Write 1 to disable interrupt 19 RX3PULSEMASK 0 Receive channel 3 pulse interrupt mask Write 1 to disable interrupt 18 RX2PULSEMASK 0 Receive channel 2 pulse interrupt mask Write 1 to disable interrupt 17 RX1PULSEMASK 0 Receive channel 1 pulse interrupt mask Write 1 to disable interrupt 16 RX0PULSEMASK 0 Receive channel 0 pulse interrupt mask Write 1 to disable interrupt 15 8...

Page 111: ...ed PEND PEND R 0 R 0 R 0 LEGEND R Read only n value after reset Table 53 MAC Interrupt Status Unmasked Register MACINTSTATRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 HOSTPEND Host pending interrupt HOSTPEND raw interrupt read before mask 0 STATPEND Statistics pending interrupt STATPEND raw interrupt read before mask 111 SPRUEF8F March 2006 Revised November 2010 C6...

Page 112: ...T Reserved PEND PEND R 0 R 0 R 0 LEGEND R W R Read only n value after reset Table 54 MAC Interrupt Status Masked Register MACINTSTATMASKED Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 HOSTPEND Host pending interrupt HOSTPEND masked interrupt read 0 STATPEND Statistics pending interrupt STATPEND masked interrupt read 112 C6472 TCI6486 EMAC MDIO SPRUEF8F March 2006 Revis...

Page 113: ... Read Write R WS Read Write 1 to set n value after reset Table 55 MAC Interrupt Mask Set Register MACINTMASKSET Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 HOSTMASK Host error interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 0 STATMASK Statistics interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 113 SPRUEF8F Mar...

Page 114: ... Read Write R WC Read Write 1 to clear n value after reset Table 56 MAC Interrupt Mask Clear Register MACINTMASKCLEAR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 HOSTMASK Host error interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 0 STATMASK Statistics interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 114 ...

Page 115: ... Receive no buffer chaining bit 0 Received frames can span multiple buffers 1 Receive DMA controller transfers each frame into a single buffer regardless of the frame or buffer size All remaining frame data after the first buffer is discarded The buffer descriptor buffer length field will contain the entire frame byte count up to 65535 bytes 27 25 Reserved 0 Reserved 24 RXCMFEN Receive copy MAC co...

Page 116: ... frames 4h Select channel 4 to receive promiscuous frames 5h Select channel 5 to receive promiscuous frames 6h Select channel 6 to receive promiscuous frames 7h Select channel 7 to receive promiscuous frames 15 14 Reserved 0 Reserved 13 RXBROADEN Receive broadcast enable Enable received broadcast frames to be copied to the channel selected by RXBROADCH bits 0 Broadcast frames are filtered 1 Broadc...

Page 117: ...ct channel 1 to receive multicast frames 2h Select channel 2 to receive multicast frames 3h Select channel 3 to receive multicast frames 4h Select channel 4 to receive multicast frames 5h Select channel 5 to receive multicast frames 6h Select channel 6 to receive multicast frames 7h Select channel 7 to receive multicast frames 117 SPRUEF8F March 2006 Revised November 2010 C6472 TCI6486 EMAC MDIO S...

Page 118: ... Receive channel 6 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 5 RXCH5EN Receive channel 5 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 4 RXCH4EN Receive channel 4 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 3 RXCH3EN Receive channel 3 unicast enable set bit Write 1 to...

Page 119: ...no effect 6 RXCH6EN Receive channel 6 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 5 RXCH5EN Receive channel 5 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 4 RXCH4EN Receive channel 4 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 3 RXCH3EN Receive channel 3 unicast enable clear bit Write 1 to cl...

Page 120: ...h Register RXMAXLEN Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 RXMAXLEN Receive maximum frame length These bits determine the maximum length of a received frame The reset value is 5EEh 1518 Frames with byte counts greater than RXMAXLEN are long frames Long frames with no errors are oversized frames Long frames with CRC code or alignment errors are jabber frames 1...

Page 121: ...FEROFFSET Receive buffer offset value These bits are written by the EMAC into each frame SOP buffer descriptor Buffer Offset field The frame data begins after the RXBUFFEROFFSET value of bytes A value of 0 indicates that there are no unused bytes at the beginning of the data and that valid data begins on the first byte of the buffer A value of Fh 15 indicates that the first 15 bytes of the buffer ...

Page 122: ...0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 62 Receive Filter Low Priority Frame Threshold Register RXFILTERLOWTHRESH Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 RXFILTERTHRESH Receive filter low threshold These bits contain the free buffer count threshold value for filtering low priority incoming frames This field should remain 0 if no filte...

Page 123: ...ved RXnFLOWTHRESH R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 63 Receive Channel n Flow Control Threshold Register RXnFLOWTHRESH Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 RXnFLOWTHRESH Receive flow threshold These bits contain the threshold value for issuing flow control on incoming frames for channel n when enabled 123 SPRUEF8F March 200...

Page 124: ...he RXFILTERTHRESH value is compared with this field to determine if low priority frames should be filtered The RXnFLOWTHRESH value is compared with this field to determine if receive flow control should be issued against incoming packets if enabled This is a write to increment field This field rolls over to zero on overflow If hardware flow control or QOS is used the host must initialize this fiel...

Page 125: ...The RGMII interface requires and uses the in band signals coming in on its receive 17 GIGFORCE Gigabit force mode This bit is used to force the EMAC into gigabit mode if the input MTCLK signal has been stopped by the PHY 16 RMIIDUPLEXMODE Duplex mode for the RMII interface 0 The RMII operates in half duplex mode This mode is not supported in the TCI6486 C6472 devices 1 The RMII operates in full du...

Page 126: ...n in full duplex mode Incoming pause frames are not acted upon in half duplex mode regardless of this bit setting The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory 0 Transmit flow control is disabled Full duplex mode incoming pause frames are not acted upon 1 Transmit flow control is enabled Full duplex mode incoming pause frames are acted upon 3 RXBUFFE...

Page 127: ...r Host error interrupts require a hardware reset in order to recover A zero packet length is an error but it is not detected 0 No error 1h SOP error the buffer is the first buffer in a packet but the SOP bit is not set in software 2h Ownership bit not set in SOP buffer 3h Zero next buffer descriptor pointer without EOP 4h Zero buffer pointer 5h Zero buffer length 6h Packet length error sum of buff...

Page 128: ...GMIIGIG RGMII gigabit This is the value of RGMIIGIG input 3 RGMIIFULLDUPLEX RGMII full duplex This is the value of RGMIIFULLDUPLEX input 2 RXQOSACT Receive Quality of Service QOS active bit When asserted indicates that receive quality of service is enabled and that at least one channel freebuffer count RXnFREEBUFFER is less than or equal to the RXFILTERLOWTHRESH value 0 Receive quality of service ...

Page 129: ...d R 0 15 2 1 0 Reserved SOFT FREE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 67 Emulation Control Register EMCONTROL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 SOFT Emulation soft bit 0 FREE Emulation free bit 129 SPRUEF8F March 2006 Revised November 2010 C6472 TCI6486 EMAC MDIO Submit Documentation Feedback Copyright 2006 2010 Texas ...

Page 130: ...Occupancy of the receive FIFO when Receive FIFO flow control is triggered if enabled The default value is 0x2 which means that receive FIFO flow control is triggered when the occupancy of the FIFO reaches two cells 15 5 Reserved 0 Reserved 4 0 TXCELLTHRESH Transmit FIFO cell threshold Indicates the number of 64 byte packet cells required to be in the transmit FIFO before the packet transfer is ini...

Page 131: ... n value after reset Table 69 MAC Configuration Register MACCONFIG Field Descriptions Bit Field Value Description 31 24 TXCELLDEPTH Transmit cell depth These bits indicate the number of cells in the transmit FIFO 23 16 RXCELLDEPTH Receive cell depth These bits indicate the number of cells in the receive FIFO 15 8 ADDRESSTYPE Address type 7 0 MACCFIG MAC configuration value 131 SPRUEF8F March 2006 ...

Page 132: ...SOFTRESET Software reset Writing a one to this bit causes the EMAC logic to be reset Software reset occurs when the receive and transmit DMA controllers are in an idle state to avoid locking up the Configuration bus After writing a one to this bit it may be polled to determine if the reset has occurred If a one is read the reset has not yet occurred If a zero is read then reset has occurred 0 A so...

Page 133: ...MACSRCADDR0 MACSRCADDR1 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 71 MAC Source Address Low Bytes Register MACSRCADDRLO Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 8 MACSRCADDR0 MAC source address lower 8 bits byte 0 7 0 MACSRCADDR1 MAC source address bits 15 8 byte 1 133 SPRUEF8F March 2006 Revised November 2010 C6472 TCI6486 EMAC MDIO...

Page 134: ...W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 72 MAC Source Address High Bytes Register MACSRCADDRHI Field Descriptions Bit Field Value Description 31 24 MACSRCADDR2 MAC source address bits 23 16 byte 2 23 16 MACSRCADDR3 MAC source address bits 31 24 byte 3 15 8 MACSRCADDR4 MAC source address bits 39 32 byte 4 7 0 MACSRCADDR5 MAC source address bits 47 40 byte 5 134 C6472 T...

Page 135: ...0 XOR DA 46 Hash_fun 5 DA 5 XOR DA 11 XOR DA 17 XOR DA 23 XOR DA 29 XOR DA 35 XOR DA 41 XOR DA 47 This function is used as an offset into a 64 bit hash table stored in MACHASH1 and MACHASH2 that indicates whether a particular address should be accepted or not The MAC hash address register 1 MACHASH1 is shown in Figure 79 and described in Table 73 Figure 79 MAC Hash Address Register 1 MACHASH1 31 1...

Page 136: ...W Read Write n value after reset Table 74 MAC Hash Address Register 2 MACHASH2 Field Descriptions Bit Field Value Description 31 0 MACHASH2 Most significant 32 bits of the hash table corresponding to hash values 32 to 63 If a hash table bit is set then a group address that hashes to that bit index is accepted 136 C6472 TCI6486 EMAC MDIO SPRUEF8F March 2006 Revised November 2010 Submit Documentatio...

Page 137: ...m Number Generator to be read Reading this field returns the generator s current value The value is reset to zero and begins counting on the clock after the de assertion of reset 15 12 COLLCOUNT Collision count These bits indicate the number of collisions the current frame has experienced 11 10 Reserved 0 Reserved 9 0 TXBACKOFF Back off count This field allows the current value of the back off cou...

Page 138: ...icates that transmit pacing is active A transmit frame collision or deferral causes PACEVAL to be loaded with 1Fh 31 good frame transmissions with no collisions or deferrals cause PACEVAL to be decremented down to 0 When PACEVAL is nonzero the transmitter delays four Inter Packet Gaps between new frame transmissions after each successfully transmitted frame that had no deferrals or collisions If a...

Page 139: ...Reserved 0 Reserved 15 0 PAUSETIMER Receive pause timer value These bits allow the contents of the receive pause timer to be observed The receive pause timer is loaded with FF00h when the EMAC sends an outgoing pause frame with pause time of FFFFh The receive pause timer is decremented at slot time intervals If the receive pause timer decrements to 0 then another outgoing pause frame is sent and t...

Page 140: ...er TXPAUSE Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 PAUSETIMER Transmit pause timer value These bits allow the contents of the transmit pause timer to be observed The transmit pause timer is loaded by a received incoming pause frame and then decremented at slot time intervals down to 0 at which time EMAC transmit frames are again enabled 140 C6472 TCI6486 EMAC ...

Page 141: ...not be used in determining whether or not an incoming packet matches or is filtered 1 Address location is valid and will be used in determining whether or not an incoming packet matches or is filtered 19 MATCHFILT Match or filter bit 0 The address will be used if VALID is set to determine if the incoming packet address should be filtered 1 The address will be used if VALID is set to determine if t...

Page 142: ...R W 0 LEGEND R W Read Write n value after reset Table 80 MAC Address High Bytes Register MACADDRHI Field Descriptions Bit Field Value Description 31 24 MACADDR2 MAC source address bits 23 16 byte 2 23 16 MACADDR3 MAC source address bits 31 24 byte 3 15 8 MACADDR4 MAC source address bits 39 32 byte 4 7 0 MACADDR5 MAC source address bits 47 40 byte 5 142 C6472 TCI6486 EMAC MDIO SPRUEF8F March 2006 R...

Page 143: ... Value Description 31 5 Reserved 0 Reserved 4 0 MACINDEX MAC address index The host must write the index into the RX ADDR RAM in the MACINDEX field followed by the upper 32 bits of address followed by the lower 16 bits of address with control bits The 53 bit indexed ram location is written when the low location is written All 32 address RAM locations must be initialized prior to enabling packet re...

Page 144: ...nel n DMA Head Descriptor Pointer Register TXnHDP Field Descriptions Bit Field Value Description 31 0 TXnHDP Transmit channel n DMA Head Descriptor pointer Writing a transmit DMA buffer descriptor address to a head pointer location initiates transmit DMA operations in the queue for the selected channel Writing to these locations when they are nonzero is an error except at reset Host software must ...

Page 145: ...n DMA Head Descriptor Pointer Register RXnHDP Field Descriptions Bit Field Value Description 31 0 RXnHDP Receive channel n DMA Head Descriptor pointer Writing a receive DMA buffer descriptor address to this location allows receive DMA operations in the selected channel when a channel frame is received Writing to these locations when they are nonzero is an error except at reset Host software must i...

Page 146: ...eset Table 84 Transmit Channel n Completion Pointer Register TXnCP Field Descriptions Bit Field Value Description 31 0 TXnCP Transmit channel n completion pointer register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The EMAC uses the value written to determine if the interrupt should be de asserted 146 C6472 TCI648...

Page 147: ...eset Table 85 Receive Channel n Completion Pointer Register RXnCP Field Descriptions Bit Field Value Description 31 0 RXnCP Receive channel n completion pointer register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The EMAC uses the value written to determine if the interrupt should be de asserted 147 SPRUEF8F March...

Page 148: ...s shown in Figure 92 and described in Table 86 Figure 92 Statistics Register 31 16 COUNT R W 0 15 0 COUNT R W 0 LEGEND R W Read Write n value after reset Table 86 Statistics Register Field Descriptions Bit Field Value Description 31 0 COUNT Count 5 50 1 Good Receive Frames Register RXGOODFRAMES The total number of good frames received on the EMAC A good frame is defined as having all of the follow...

Page 149: ... any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no alignment or code error Had a CRC error A CRC error is defined as having all of the following A frame containing an even number of nibbles Fails the frame check sequence test See Section 2 5 5 for definitions of alignment and co...

Page 150: ... Overruns have no effect on this statistic 5 50 9 Receive Undersized Frames Register RXUNDERSIZED The total number of undersized frames received on the EMAC An undersized frame is defined as having all of the following Was any data frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was less than 64 bytes long Had no CRC error alignment error or code erro...

Page 151: ...aving all of the following Any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode The frame destination channel flow control threshold register RXnFLOWTHRESH value was greater than or equal to the channel s corresponding free buffer register RXnFREEBUFFER value Was of length 64 to RXMAXLEN RXQOSEN bit is set in RXMBPENABLE Had no CRC ...

Page 152: ...s Register TXDEFERRED The total number of frames transmitted on the EMAC that first experienced deferment Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcast or multicast address Was any size Had no carrier loss and no underrun Experienced no collisions before being successfully transmitted Found the medium busy when transmiss...

Page 153: ...ore abandoning all attempts at transmitting the frame None of the collisions were late CRC errors have no effect on this statistic 5 50 23 Transmit Late Collision Frames Register TXLATECOLL The total number of frames when transmission was abandoned due to a late collision Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcast or ...

Page 154: ...mitted and experienced carrier loss that resulted in a frame of this size being transmitted then the frame is recorded in this statistic CRC errors alignment code errors and overruns do not affect the recording of frames in this statistic 5 50 28 Transmit and Receive 65 to 127 Octet Frames Register FRAME65T127 The total number of 65 byte to 127 byte frames received and transmitted on the EMAC Such...

Page 155: ...rame is defined as having all of the following Any data or MAC control frame that was destined for any unicast broadcast or multicast address Did not experience late collisions excessive collisions underrun or carrier sense error Was 1024 bytes to RXMAXLEN bytes long CRC alignment code errors underruns and overruns do not affect frame recording in this statistic 5 50 33 Network Octet Frames Regist...

Page 156: ...omiscuous mode Was of any size including less than 64 byte and greater than RXMAXLEN byte frames The EMAC was unable to receive it because it did not have the resources to receive it cell FIFO full or no DMA buffer available after the frame was successfully started no SOF overrun CRC errors alignment errors and code errors have no effect on this statistic 5 50 36 Receive DMA Start of Frame and Mid...

Page 157: ...um in this mode Full duplex mode can only be used when all of the following are true The physical medium is capable of supporting simultaneous transmission and reception without interference There are exactly two stations connected with a full duplex point to point link As there is no contention for use of a shared medium the multiple access i e CSMA CD algorithms are unnecessary Both stations on ...

Page 158: ...t technologies a simple three field type notation is used The Physical Layer type used by the Ethernet is specified by these fields data rate in Mb s medium type maximum segment length 100m The definitions for the technologies mentioned in this guide are as follows Term Definition 10Base T IEEE 802 3 Physical Layer specification for a 10 Mb s CSMA CD local area network over two pairs of twisted pa...

Page 159: ...ified TXINTMASKCLEAR register figure Table 46 Modified TXINTMASKCLEAR register table Figure 57 Modified RXINTMASKSET register figure Table 51 Modified RXINTMASKSET register table Figure 58 Modified RXINTMASKCLEAR register figure Table 52 Modified RXINTMASKCLEAR register table 159 SPRUEF8F March 2006 Revised November 2010 Revision History Submit Documentation Feedback Copyright 2006 2010 Texas Inst...

Page 160: ...ch statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications o...

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