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Preface
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10
1
Introduction
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11
1.1
Purpose of the Peripheral
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11
1.2
Features
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11
1.3
Functional Block Diagram
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12
1.4
Industry Standard(s) Compliance Statement
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14
2
EMAC Functional Architecture
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15
2.1
Clock Control
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15
2.2
Memory Map
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16
2.3
System-Level Connections
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17
2.4
Ethernet Protocol Overview
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29
2.5
Programming Interface
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31
2.6
Communications Port Programming Interface (CPPI)
............................................................
40
2.7
Ethernet Multicore Interrupt Combiner (EMIC) Module
...........................................................
40
2.8
Management Data Input/Output (MDIO) Module
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47
2.9
EMAC Module
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52
2.10
Media Independent Interfaces
........................................................................................
54
2.11
Packet Receive Operation
............................................................................................
58
2.12
Packet Transmit Operation
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62
2.13
Receive and Transmit Latency
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63
2.14
Transfer Node Priority
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63
2.15
Reset Considerations
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64
2.16
Initialization
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65
2.17
Interrupt Support
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67
2.18
Power Management
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69
2.19
Emulation Considerations
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69
3
EMIC Module Registers
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71
3.1
EW_INTCTL Registers
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71
3.2
RPIC Registers
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71
3.3
TPIC Registers
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74
3.4
Prescalar Configuration Register (PSCFG)
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75
4
MDIO Registers
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76
4.1
Introduction
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76
4.2
MDIO Version Register (VERSION)
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77
4.3
MDIO Control Register (CONTROL)
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78
4.4
PHY Acknowledge Status Register (ALIVE)
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79
4.5
PHY Link Status Register (LINK)
....................................................................................
80
4.6
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
...................................
81
4.7
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
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82
4.8
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
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83
4.9
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
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84
4.10
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
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85
3
SPRUEF8F – March 2006 – Revised November 2010
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