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SRIO Functional Description

Table 25. Emulation Control Signals

Name

Bit

Access

Reset Value

Description

Free

0

R/W

1b

FREE = 0, SOFT Bit takes effect

FREE = 1, Free run mode (default mode) - Peripheral ignores the
EMUSUSP signal and functions normally.

Soft

1

R/W

0b

SOFT = 0 -> Soft Stop (default mode)

SOFT = 1 -> Hard stop – All status registers are frozen in default state.
(Mode not supported)

PEREN

2

R/W

0b

Peripheral Enable.

0b – Disabled

1b – Enabled

Reserved

31:3

0b

Reserved

Free Run Mode: (default mode) Peripheral does not respond to EMUSUSP assertion. Module functions
normally, irrespective of CPU emulation state.

Soft Stop Mode: Peripheral gracefully halts operations. The peripheral halts operation at a point that
makes sense both to the internal DMA/data access operation and to the pin interface as described below,
after finishing packet reception or transmission in progress:

•

DMA bus DMA master: DMA bus requests in progress are allowed to complete (DMA bus has no
means to throttle command in progress from the Master) DMA bus requests that correspond to the
same network packet are allowed to complete. No new DMA bus requests will be generated on the
next new packet.

•

Configuration bus MMR interface: All MMR configuration bus requests are serviced as normal.

•

Events/interrupts: New events/interrupts are not generated to the CPU for newly arriving packets.
Current transactions are allowed to finish and may cause an interrupt upon completion.

•

Slave pin interface: The pin interface functions as normal. If buffering is available in the peripheral,
the peripheral services externally generated requests as long as possible. When the internal buffers
are consumed, the peripheral will retry incoming network packets in the physical layer.

•

Master pin interface: No new master requests are generated. Master requests in progress are
allowed to complete, including all packets located in the physical layer transmit buffers.

Hard Stop Mode: Peripheral should halt immediately. This mode is not supported in the RapidIO
peripheral.

2.3.11

Initialization Example

2.3.11.1

Enabling the SRIO Peripherals

When the device is powered on, the SRIO peripheral is in a disabled state. Before any SRIO specific
initialization can take place, the peripheral needs to be enabled; otherwise, its registers cannot be written,
and the reads will all return a value of zero.

/* Glb enable srio */

SRIO_REGS->GBL_EN

= 0x00000001 ;

SRIO_REGS->BLK0_EN

= 0x00000001 ;

//MMR_EN

SRIO_REGS->BLK5_EN

= 0x00000001 ;

//PORT0_EN

SRIO_REGS->BLK1_EN

= 0x00000001 ;

//LSU_EN

SRIO_REGS->BLK2_EN

= 0x00000001 ;

//MAU_EN

SRIO_REGS->BLK3_EN

= 0x00000001 ;

//TXU_EN

SRIO_REGS->BLK4_EN

= 0x00000001 ;

//RXU_EN

SRIO_REGS->BLK6_EN

= 0x00000001 ;

//PORT1_EN

SRIO_REGS->BLK7_EN

= 0x00000001 ;

//PORT2_EN

SRIO_REGS->BLK8_EN

= 0x00000001 ;

//PORT3_EN

SPRU976 – March 2006

Serial RapidIO (SRIO)

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Summary of Contents for TMS320C645X

Page 1: ...TMS320C645x Serial Rapid IO SRIO User s Guide Literature Number SPRU976 March 2006 ...

Page 2: ...2 SPRU976 March 2006 Submit Documentation Feedback ...

Page 3: ... n Enable Status Register BLKn_EN_STAT 107 5 9 RapidIO DEVICEID1 Register DEVICEID_REG1 108 5 10 RapidIO DEVICEID2 Register DEVICEID_REG2 109 5 11 Packet Forwarding Register n for 16b DeviceIDs PF_16B_CNTLn 110 5 12 Packet Forwarding Register n for 8b DeviceIDs PF_8B_CNTLn 111 5 13 SERDES Receive Channel Configuration Registers n SERDES_CFGRXn_CNTL 112 5 14 SERDES Transmit Channel Configuration Re...

Page 4: ...n_REG4 146 5 46 LSUn Control Register 5 LSUn_REG5 147 5 47 LSUn Control Register 6 LSUn_REG6 148 5 48 LSU Congestion Control Flow Mask n LSU_FLOW_MASKS n 149 5 49 Queue Transmit DMA Head Descriptor Pointer Registers QUEUEn_TXDMA_HDP 150 5 50 Queue Transmit DMA Completion Pointer Registers QUEUEn_TXDMA_CP 151 5 51 Queue Receive DMA Head Descriptor Pointer Registers QUEUEn_RXDMA_HDP 152 5 52 Queue R...

Page 5: ...ce ID Capture CSR ID_CAPT 195 5 92 Logical Transport Layer Control Capture CSR CTRL_CAPT 196 5 93 Port Write Target Device ID CSR PW_TGT_ID 197 5 94 Port Error Detect CSR n SPn_ERR_DET 198 5 95 Port Error Rate Enable CSR n SPn_RATE_EN 199 5 96 Port n Attributes Error Capture CSR 0 SPn_ERR_ATTR_CAPT_DBG0 200 5 97 Port n Packet Control Symbol Error Capture CSR 1 SPn_ERR_CAPT_DBG1 201 5 98 Port n Pac...

Page 6: ...tor 57 25 TX Buffer Descriptor 58 26 Doorbell Operation 59 27 Flow Control Table Entry Registers Address Offset 0x0900 0x093C 61 28 Transmit Source Flow Control Masks 62 29 Configuration Bus Example 63 30 DMA Example 64 31 GBL_EN Address 0x0030 65 32 GBL_EN_STAT Address 0x0034 65 33 BLK0_EN Address 0x0038 65 34 BLK0_EN_STAT Address 0x003C 66 35 BLK1_EN Address 0x0040 66 36 BLK1_EN_STAT Address 0x0...

Page 7: ...rrupt Register LSU _ICCR 124 80 Error Reset and Special Event Status Interrupt Register ERR_RST_EVNT_ICSR 125 81 Error Reset and Special Event Clear Interrupt Register ERR_RST_EVNT_ICCR 126 82 DOORBELLn Interrupt Condition Routing Register DOORBELLn_ICRR 127 83 DOORBELLn Interrupt Condition Routing Register 2 DOORBELLn_ICRR2 128 84 RX CPPI Interrupt Condition Routing Register RX_CPPI _ICRR 129 85 ...

Page 8: ...se Address 1 CSR LCL_CFG_BAR 175 130 Base Device ID CSR BASE_ID 176 131 Host Base Device ID Lock CSR HOST_BASE_ID_LOCK 177 132 Component Tag CSR COMP_TAG 178 133 1x 4x LP_Serial Port Maintenance Block Header Register SP_MB_HEAD 179 134 Port Link Time Out Control CSR SP_LT_CTL 180 135 Port Response Time Out Control CSR SP_RT_CTL 181 136 Port General Control CSR SP_GEN_CTL 182 137 Port Link Maintena...

Page 9: ...0 162 Port Write In Capture CSR n SP_IP_PW_IN_CAPTn 211 163 Port Reset Option CSR n SPn_RST_OPT 212 164 Port Control Independent Register n SPn_CTL_INDEP 213 165 Port Silence Timer n SPn_SILENCE_TIMER 215 166 Port Multicast Event Control Symbol Request Register n SPn_MULT_EVNT_CS 216 167 Port Control Symbol Transmit n SPn_CS_TX 217 SPRU976 March 2006 List of Figures 9 Submit Documentation Feedback...

Page 10: ... Register PID Field Descriptions 99 30 Peripheral Control Register PCR Field Descriptions 100 31 Peripheral Settings Control Register PER_SET_CNTL Field Descriptions 101 32 Peripheral Global Enable Register GBL_EN Field Descriptions 104 33 Peripheral Global Enable Status Register GBL_EN_STAT Field Descriptions 105 34 Block n Enable Register BLKn_EN Field Descriptions 106 35 Block n Enable Status R...

Page 11: ...ptions 142 72 LSUn Control Register 1 LSUn_REG1 Field Descriptions 143 73 LSUn Control Register 2 LSUn_REG2 Field Descriptions 144 74 LSUn Control Register 3 LSUn_REG3 Field Descriptions 145 75 LSUn Control Register 4 LSUn_REG4 Field Descriptions 146 76 LSUn Control Register 5 LSUn_REG5 Field Descriptions 147 77 LSUn Control Register 6 LSUn_REG6 Field Descriptions 148 78 LSU Congestion Control Flo...

Page 12: ...dress Capture CSR ADDR_CAPT Field Descriptions 194 121 Logical Transport Layer Device ID Capture CSR ID_CAPT Field Descriptions 195 122 Logical Transport Layer Control Capture CSR CTRL_CAPT Field Descriptions 196 123 Port Write Target Device ID CSR PW_TGT_ID Field Descriptions 197 124 Port Error Detect CSR n SPn_ERR_DET Field Descriptions 198 125 Port Error Rate Enable CSR n SPn_RATE_EN Field Desc...

Page 13: ...965 gives an introduction to the TMS320C6455 DSP and discusses the application areas that are enhanced TMS320C6000 Programmer s Guide literature number SPRU198 describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples TMS320C6000 Code Composer Studio Tutorial literature number SPRU301 introduces the Code Composer Studio integrated development...

Page 14: ...puting Principle features of RapidIO include Flexible system architecture allowing peer to peer communication Robust communication with error detection features Frequency and port width scalability Operation that is not software intensive High bandwidth interconnect with low overhead Low pin count Low power Low latency 1 1 1 RapidIO Architectural Hierarchy RapidIO is defined as a 3 layer architect...

Page 15: ... address Information to transport packet from end Transport specification spec transport Common between two physical devices i e electrical Information necessary to move packet interface flow control Physical specification 1x 4x LP serial LP LVDS 8 16 Future spec physical checklist Compliance Inter operability specification Overview Figure 1 RapidIO Architectural Hierarchy SPRU976 March 2006 Seria...

Page 16: ...LP LVDS specification is a point to point synchronous clock sourcing DDR interface The 1X 4X LP Serial specification is a point to point AC coupled clock recovery interface The two physical layer specifications are not compatible SRIO complies with the 1X 4X LP Serial specification The serializer deserializer SERDES technology in SRIO also aligns with that specification The 1X 4X LP Serial specifi...

Page 17: ...rential CML signaling supporting AC and DC coupling Support for 1 25 2 5 and 3 125 Gbps rates Power down option for unused ports Read write write with response streaming write outgoing Atomic and maintenance operations Generates interrupts to the CPU Doorbell packets and internal scheduling Support for 8b and 16b device ID Support for receiving 34b addresses Support for generating 34b 50b and 66b ...

Page 18: ... 2 of the RapidIO Interconnect Specification and V1 2 of the LP Serial specification Table 1 RapidIO Documents and Links Document Link Description Official RapidIO Web Site http www RapidIO org Various associated docs SRIO provides a seamless interface to all devices which are compliant to V1 2 of the LP Serial RapidIO specification This includes ASIC microprocessor DSP and switch fabric devices f...

Page 19: ...lained using the high level block diagram shown in Figure 4 High speed data enters from the device pins into the RX block of the SERDES macro The RX block is a differential receiver expecting a minimum of 175mV peak to peak differential input voltage Vid Level shifting is performed in the RX block such that the output is single ended CMOS The serial data is then fed to the SERDES clock recovery bl...

Page 20: ...ng used The FIFO is 8 words deep The lane de skew is only meaningful in the 4X mode where it aligns each channel s word boundaries such that the resulting 32 bit word is correctly aligned The CRC error detection block keeps a running tally of the incoming data and computes the expected CRC value for the 1X or 4X mode The expected value is compared against the CRC value at the end of the received p...

Page 21: ...Figure 5 shows how a packet progresses through the system Figure 5 Operation Sequence 2 1 2 2 Example Packet Streaming Write An example packet is shown as two data streams in Figure 6 The first is for payload sizes of 80 bytes or less while the second applies to payload sizes of 80 to 256 bytes SRIO packets must have a length that is an even integer of 32 bits If the combination of physical logica...

Page 22: ... Accepted control symbol is sent by the receiving device If the CRC is incorrect a Packet Not Accepted control symbol is sent so that transmission may be retried 2 1 2 3 Control Symbols Control symbols are physical layer message elements used to manage link maintenance packet delimiting packet acknowledgment error reporting and error recovery All transmitted data packets are delimited by start of ...

Page 23: ...110b Atomic t s Ttype others Ftype 6 Ttype don t care SWRITE Ftype 7 Ttype don t care Congestion Ftype 8 Ttype 0000b Mtn Rd Ttype 0001b Mtn Wr Ttype 0010b Mtn Rd Resp Ttype 0011b Mtn Wr Resp Ttype 0100b Mtn Pt Wr Ttype others Ftype 10 Ttype don t care Doorbell Ftype 11 Ttype don t care Message Ftype 13 Ttype 0000b Resp Dbll Resp Ttype 0001b Message Resp Ttype 1000b Resp w payload Ttype other Undef...

Page 24: ... Data Differential point to point unidirectional bus Receives packet data for a transmitting device s TX pins Most significant bits in 4X mode RIORX2 RIORX2 2 Input Receive Data Differential point to point unidirectional bus Receives packet data for a transmitting device s TX pins RIORX1 RIORX1 2 Input Receive Data Differential point to point unidirectional bus Receives packet data for a transmitt...

Page 25: ...6B 8 buffers per 1X port all priorities 32 buffers per 4X port 8 per priority Transaction mapping layer buffers Logical Load store unit LSU Tx direct I O Maintenance Messaging TXU Rx direct I O MAU Memory access unit RXU Messaging buffer 4 5 KB Tx shared buffer shared 4 5 KB Tx handle Queue 128 bit DMA bus 128 bit SRIO Functional Description Figure 8 SRIO Conceptual Block Diagram SPRU976 March 200...

Page 26: ...ers contain on chip termination resistors The only off chip component requirement is for DC blocking capacitors These capacitors are needed only to ensure interoperability between vendors and can be removed in cases where TI devices talk to other TI devices at the same voltage node The SERDES are designed for 1 2V 5 operation This provides for excellent power efficiency 2 3 2 1 Enabling the PLL Th...

Page 27: ...2x GHz 2 RIOCLK and RIOCLKFREQ LINERATE RATESCALE MPY The rate is defined by the RATE bits of the SERDES_CFGRXn_CNTL register and the SERDES_CFGTXn_CNTL register respectively The primary operating frequency of the SERDES macro is determined by the reference clock frequency and PLL multiplication factor However to support lower frequency applications each receiver and transmitter can also be config...

Page 28: ... Reserved Reserved keep as zero during writes to this register 24 Reserved Reserved keep as zero during writes to this register 23 Reserved Reserved 22 19 EQ Equalizer Enables and configures the adaptive equalizer to compensate for loss in the transmission media For values see Table 9 18 16 CDR Clock data recovery Configures the clock data recovery algorithm 000 First order Phase offset tracking u...

Page 29: ...mmon point set to 0 8 VDDT This configuration is for AC coupled systems using CML transmitters The transmitter has no effect on the receiver common mode which is set to optimize the input sensitivity of the receiver Common mode termination is via a 50 pF capacitor to VSSA 010 Reserved 011 Common point floating This configuration is for DC coupled systems that require the common mode voltage to be ...

Page 30: ...p of TXBCLKINn with respect to TXBCLKn 0 Arbitrary phase No required phase relationship between TXBCLKINn and TXBCLKn 1 Fixed phase Requires direct connection of TXBCLKn to TXBCLKINn using a minimum length net without buffers 15 12 DE De emphasis Selects one of 15 output de emphasis settings from 4 76 to 71 42 See Table 12 11 9 SWING Output swing Selects one of 8 output amplitude settings between ...

Page 31: ...ignored 01x Reserved 1xx Reserved 1 Reserved Reserved 0 ENTX Enable transmitter Enables this transmitter when high Table 11 SWING Bits CFGTX 11 9 Amplitude mVdfpp 000 125 001 250 010 500 011 625 100 750 101 1000 110 1125 111 1250 Table 12 DE Bits CFGTX 15 12 Amplitude Reduction dB 0000 0 0 0001 4 76 0 42 0010 9 52 0 87 0011 14 28 1 34 0100 19 04 1 83 0101 23 8 2 36 0110 28 56 2 92 0111 33 32 3 52 ...

Page 32: ... ASIC is talking with DSP the ASIC will have destination circular buffer description tables that contain DSP addresses buffer sizes and write pointer information These tables are initialized by the DSP upon system boot after the initialization discovery phase Updates to the table could be managed completely by the DSP through RapidIO master writes Once these tables are established the ASIC RapidIO...

Page 33: ...ed RapidIO packet header address 2 24b Config_offset Field Maintenance Packets Type 8 Will be used in conjunction with BYTE_COUNT to create 64b aligned RapidIO packet header Config_offset The 2 LSB of this field must be zero since the smallest configuration access is 4B DSP Address 32b DSP byte address Not available in RapidIO Header Byte_Count Number of data bytes to Read Write up to 4KB Used in ...

Page 34: ...ror 100b Transaction complete packet not sent due to unsupported transaction type or invalid programming encoding for one or more LSU register fields 101b DMA data transfer error 110b Retry DOORBELL response received or Atomic Test and swap was not allowed semaphore in use 111b Transaction complete packet not sent due to unavailable outbound credit at given priority 1 1 Status available only when ...

Page 35: ...1_Reg2 CSL_FMK SRIO_LSU1_REG2_DSP_ADDRESS int xmtBuff1 0 SRIO_REGS LSU1_Reg3 CSL_FMK SRIO_LSU1_REG3_BYTE_COUNT byte_count SRIO_REGS LSU1_Reg4 CSL_FMK SRIO_LSU1_REG4_OUTPORTID 0 CSL_FMK SRIO_LSU1_REG4_PRIORITY 0 CSL_FMK SRIO_LSU1_REG4_XAMBS 0 no extended address CSL_FMK SRIO_LSU1_REG4_ID_SIZE 1 tt 0b01 CSL_FMK SRIO_LSU1_REG4_DESTID 0xBEEF CSL_FMK SRIO_LSU1_REG4_INTERRUPT_REQ 1 0 event driven 1 poll...

Page 36: ...are generated through this interface The data path for this module uses DMA bus as the DMA interface The configuration bus is used by the CPU to access the control command registers The registers contain transfer descriptors that are needed to initiate READ and WRITE packet generation After the transfer descriptors are written flow control status is queried The unit examines the DESTID and PRIORIT...

Page 37: ...te that only one payload can be completed in any single DMA bus cycle The Load Store module can only forward the packet to the TX FIFO after the final payload byte from the DMA bus response has been written into the shared memory buffer Once the packet is forwarded to the TX FIFO the shared buffer can be released and made available for a new transaction The TX buffer space is dynamically shared am...

Page 38: ...oad DMA bus response writes data to specified module buffer in the shared TX buffer space DMA bus read response is monitored for last byte of payload Header data in the LSU registers is written to the shared TX buffer space Payload and header are transferred to the TX FIFO The LSU registers are released if no RapidIO response is needed Transfer from the TX FIFO to external device based on priority...

Page 39: ...sponse Time out Control CSR value discussed in sections 5 10 1 and 6 1 2 4 of the serial specification If the time expires control command register resources should be released and an error is logged in the ERROR MANAGEMENT RapidIO registers The RapidIO specification states that the maximum time interval all 1s is between 3 and 6 seconds A logical layer timeout occurs if the response packet is not...

Page 40: ...message passing is that the source device does not require any knowledge of the destination device s memory map The DSP contains Buffer Descriptions Tables for each mailbox These tables define a memory map and pointers for each mailbox Messages are transferred to the appropriate memory locations via the DMA The CPPI Communications Port Programming Interface module serves as the incoming and outgoi...

Page 41: ...g accurate state information that is needed for future processing For instance if a message spans multiple packets information must be saved that allows re assembly of those packets by the CPU The CPPI module provides a scheme for tracking single and multi packet messages linking messages in queues and generating interrupts Figure 14 illustrates the scheme Figure 14 CPPI RX Scheme for RapidIO Mess...

Page 42: ...d will not be used to match for this queue mapping entry For example a mailbox mask of all zeros would allow a mapping entry to be used for all incoming mailboxes The mapping table entry also provides a security feature to enable or disable access from specific external devices to local mailboxes The SOURCEID field indicates which external device has access to the mapping entry and corresponding q...

Page 43: ...SAR operations per core In this case a buffer descriptor queue is allocated for each desired simultaneous message The peripheral supports a total of 16 assignable RX queues and their associated RX DMA state registers Each of the queues can be assigned to single or multi segment messages Table 15 and Table 16 show the RX DMA State Registers Table 15 RX DMA State Head Descriptor Pointer HDP Address ...

Page 44: ...and is analogous to the request to response timer discussed in the TX CPPI and LSU sections which is defined by the 24 bit value in the port response time out CSR The RapidIO specification states that the maximum time interval all 1s is between 3 and 6 seconds Each multi segment receive timer requires a 4 bit register The register is loaded with the current timecode when the response is sent Each ...

Page 45: ... port determines the end of queue condition by a zero next_descriptor_pointer 0 The RX queue has more buffers available for reception 1 The Descriptor buffer is the last buffer in the last message in the queue Teardown_Complete Teardown Complete Set by the port to indicate that the host commanded teardown process is complete and the channel buffers may be reclaimed by the host 0 The port has not c...

Page 46: ...resources subsequent pipelined messages may arrive just as resources are freed up This is a problem for systems requiring in order message delivery In this case the peripheral needs to record the Src_id mailbox letter of the first retried message and retry all subsequent new requests until resources are available and a segment for that Src_id mailbox letter is received As long as all messages are ...

Page 47: ...essage to properly store the segments in memory The number of simultaneous transactions supported directly impacts the number of states to be stored and the size of the buffer descriptor memory outside the peripheral With this in mind the peripheral s supported buffer descriptor SRAM is parameterizable A minimum size of 1 25KB is recommended which will allow up to 64 buffer descriptors to be store...

Page 48: ... of the buffer descriptor are invalid The peripheral completes the teardown procedure by clearing the HDP register setting the CP register to 0xfffffffC and issuing an interrupt for the given queue The teardown command register bit is automatically cleared by the peripheral If the queue is not in message but inactive next descriptor unavailable then no additional buffer descriptor will be written ...

Page 49: ...tions and is zeroed by the port when all packets in the queue have been transmitted An error condition results if the host writes this field when the current field value is nonzero The address must be 32 bit word aligned Table 19 TX DMA State Completion Pointer CP Address Offset 0x580 0x5BC Bit Name Description 31 0 TX Queue Tx Queue Completion Pointer This field is the host memory address for the...

Page 50: ...etried 000000b Infinite Retries 000001b Retry Message 1 time 000002b Retry Message 2 times 111111b Retry Message 63 times cc Completion Code 000 Good Completion Message received a done response 001 Transaction error Message received an error response 010 Excessive Retries Message received more than retry_count retry responses 011 Transaction timeout Transaction timer elapsed without any message re...

Page 51: ...ostponed so that the TX buffer space is not wasted Because buffer descriptors cannot be reordered in the link list if the transaction at the head of the buffer descriptor queue is flow controlled HOL blocking will occur on that queue When this occurs all transactions located in that queue are stalled To counter the affects and reduce back up of more TX packets multiple queues are available The per...

Page 52: ... a Queue programmable to any of the 16 TX queues TX_Queue_Map3 31 24 R W 0x03 31 28 Number of contiguous messages descriptors to process before moving to TX_Queue_Map4 27 24 Pointer to a Queue programmable to any of the 16 TX queues TX_Queue_Map4 7 0 R W 0x04 7 4 Number of contiguous messages descriptors to process before moving to TX_Queue_Map5 3 0 Pointer to a Queue programmable to any of the 16...

Page 53: ...etry the packet before continuing to the next queue in the round robin as long as the RETRY_COUNT is not exceeded Once this limit is exceeded the buffer can be released back to CPU control with the appropriate CC set Retry of a message segment does not imply retrying a whole message Only segments for which a RETRY response is received should be re transmitted This will involve calculating the corr...

Page 54: ...ain unchanged An interrupt is not issued The teardown command register bit is automatically cleared by the peripheral Because of topology differences between flow s response packets may arrive in a different order to the order of requests After the teardown process is complete and the interrupt is serviced by the CPU software must re initialize the TX queue to restart normal operation 2 3 4 3 Deta...

Page 55: ...ocess corresponding queue until ownership 1 or eoq 1 Sets processed buffer descriptor ownership 1 Writes CP value of last buffer descriptor processed Port hardware clears ICSR bit only if the CP value written by CPU equals port written value in the RX DMA State CP register Resets interrupt pacing value TX Operation Sets up associated buffer descriptor memory CPPI RAM or L2 RAM Link lists the buffe...

Page 56: ...r Descriptor RX_DESCP0_0 RXDESC0 CSL_FMK SRIO_RXDESC0_N_POINTER int RX_DESCP0_1 link to RX_DESCP0_1 poll mode extended address type 2 5 6 RX_DESCP0_0 RXDESC1 CSL_FMK SRIO_RXDESC1_B_POINTER int rcvBuff1 0 32bit type 2 5 6 24bit type 8 RX_DESCP0_0 RXDESC2 CSL_FMK SRIO_RXDESC2_SRC_ID 0xBEEF CSL_FMK SRIO_RXDESC2_PRI 1 CSL_FMK SRIO_RXDESC2_TT 1 CSL_FMK SRIO_RXDESC2_MAILBOX 0 RX_DESCP0_0 RXDESC3 CSL_FMK...

Page 57: ...SL_FMK SRIO_TXDESC3_TEARDOWN 0 CSL_FMK SRIO_TXDESC3_RETRY_COUNT 0 CSL_FMK SRIO_TXDESC3_CC 0 CSL_FMK SRIO_TXDESC3_MESSAGE_LENGTH MLEN_512DW TX_DESCP0_1 TXDESC0 CSL_FMK SRIO_TXDESC0_N_POINTER 0 end of message poll mode extended address type 2 5 6 TX_DESCP0_1 TXDESC1 CSL_FMK SRIO_TXDESC1_B_POINTER int xmtBuff2 0 32bit type 2 5 6 24bit type 8 TX_DESCP0_1 TXDESC2 CSL_FMK SRIO_TXDESC2_DESTID 0xBEEF CSL_...

Page 58: ...s a write operation that does not have guaranteed delivery and does not have an associated response This maintenance operation is useful for sending messages such as error indicators or status information from a device that does not contain an endpoint such as a switch The data payload is typically placed in a queue in the targeted endpoint and an interrupt is typically generated to a local proces...

Page 59: ...ation The DOORBELL packet s 16 bit INFO field indicates which DOORBELL register interrupt bit to set There are four DOORBELL registers each currently with 16 bits allowing 64 interrupt sources or circular buffers Each bit can be assigned to any core as described below by the Interrupt Condition Routing Registers Additionally each status bit is user defined for the application For instance it may b...

Page 60: ...The congested route table requirements and subsequent searches would be overwhelming if each possible DESTID and PRIORITY combination had its own entry To implement a more basic scheme the following assumptions have been made A small number of flows constitute the majority of traffic and these flows are most likely to cause congestion HOL blocking is undesired but allowable for TX CPPI queues Flow...

Page 61: ...W 0x0000 DestID of Flow 11 Flow_Cntl_ID12 15 0 R W 0x0000 DestID of Flow 12 Flow_Cntl_ID13 15 0 R W 0x0000 DestID of Flow 13 Flow_Cntl_ID14 15 0 R W 0x0000 DestID of Flow 14 Flow_Cntl_ID15 15 0 R W 0x0000 DestID of Flow 15 if all 0s this table entry represents all flows other than flows 0 14 Each transmit source including LSU or Tx CPPI queues indicates which of the 16 flows it uses by having a ma...

Page 62: ... t support Flow2 from table entry 1b TX source does support Flow2 from table entry Flow Mask 3 R W 1b 0b TX source doesn t support Flow3 from table entry 1b TX source does support Flow3 from table entry Flow Mask 4 R W 1b 0b TX source doesn t support Flow4 from table entry 1b TX source does support Flow4 from table entry Flow Mask 5 R W 1b 0b TX source doesn t support Flow5 from table entry 1b TX ...

Page 63: ...essing the local MMR space Regardless of the device memory endian configuration all configuration bus accesses are performed on 32 bit values at a fixed address position The bit positions in the 32 bit word are defined by this specification This means that a memory image which will be copied to a MMR is identical between little endian and big endian configurations Configuration bus reads are perfo...

Page 64: ...is handled independently of the registers discussed in this section The SERDES can be configured to shutdown unused links or fully shutdown SERDES TX and RX channels may be enabled disabled by writing to bit 0 of the SERDES_CFGTXn_CNTL and SERDES_CFGRXn_CNTL registers The PLL and remaining SERDES functional blocks can be controlled by writing to the ENPLL signals in the PER_SET_CNTL or SERDES_CFGn...

Page 65: ...I of the RapidIO specification Until the peripheral and its partner are fully initialized and ready for normal operation the peripheral will not send any data packets or non status control symbols GBL_EN_INIT and BLK_EN_INIT n 0 These module boundary signals are static tieoffs which control the default state of the GBL_EN and BLK_EN n 0 MMRs GBL_EN Resets all MMRs excluding Reset Ctl Values 0x0000...

Page 66: ...t reset Table 24 Enable and Enable Status Bit Field Descriptions Name Bit Access Description GBL_EN 0 R W Controls reset to all clock domains within the peripheral 0 Peripheral to be disabled held in reset clocks disabled 1 Peripheral to be enabled GBL_EN_STAT 0 9 R Indicates state of GBL_EN reset signal 0 Peripheral in reset and all clocks are off 1 Peripheral enabled and clocking BLK0_EN 0 R W C...

Page 67: ...bled held in reset clocks disabled 1 Logical block 4 enabled BLK4_EN_STAT 0 R Indicates state of BLK4_EN reset signal 0 Logical block 4 reset and clock is off 1 Logical block 4 enabled and clocking BLK5_EN 0 R W Controls reset logical block 5 which is port 0 0 Logical block 5 disabled held in reset clocks disabled 1 Logical block 5 enabled BLK5_EN_STAT 0 R Indicates state of BLK5_EN reset signal 0...

Page 68: ...hutdown procedure is complete the BLKn_EN_STAT bits and or the GBL_EN_STAT bit contain 0 The opposite is done for software controlled enabling of a logical block 1 Assert the BLK_EN signal to release the logical block from reset 2 Turn on the logical block When the full start up procedure is complete the BLKn_EN_STAT bits and or the GBL_EN_STAT bit contain 1 When using the GBL_EN to shutdown reset...

Page 69: ...pts are not generated to the CPU for newly arriving packets Current transactions are allowed to finish and may cause an interrupt upon completion Slave pin interface The pin interface functions as normal If buffering is available in the peripheral the peripheral services externally generated requests as long as possible When the internal buffers are consumed the peripheral will retry incoming netw...

Page 70: ...DES_CFGTX2_CNTL 0x00010801 enable tx rate 1 SRIO_REGS SERDES_CFGTX3_CNTL 0x00010801 enable tx rate 1 2 3 11 3 Peripheral Initializations Set Device ID Registers rdata SRIO_REGS DEVICEID_REG1 wdata 0x00ABBEEF mask 0x00FFFFFF mdata wdata mask rdata mask SRIO_REGS DEVICEID_REG1 mdata id 16b BEEF id 08b AB rdata SRIO_REGS DEVICEID_REG2 wdata 0x00ABBEEF mask 0x00FFFFFF mdata wdata mask rdata mask SRIO_...

Page 71: ...R_EN 0x00000000 disable SRIO_REGS H_ADDR_CAPT 0x00000000 clear SRIO_REGS ADDR_CAPT 0x00000000 clear SRIO_REGS ID_CAPT 0x00000000 clear SRIO_REGS CTRL_CAPT 0x00000000 clear SRIO_REGS SP_IP_MODE 0x0000003F mltc rst pw enable clear SRIO_REGS SP_IP_PW_IN_CAPT0 0x00000000 clear SRIO_REGS SP_IP_PW_IN_CAPT1 0x00000000 clear SRIO_REGS SP_IP_PW_IN_CAPT2 0x00000000 clear SRIO_REGS SP_IP_PW_IN_CAPT3 0x000000...

Page 72: ...mory base address via NWRITE 10 DSP CPU is awakened by an interrupt such as a RapidIO DOORBELL packet 11 Boot Code is executed and normal operation follows Figure 40 Bootload Operation 2 3 12 2 Bootload Data Movement The system host is responsible for writing the bootload data into the DSP s L2 memory As such bootload is only supported using the Direct I O model and not the message passing model B...

Page 73: ...0b R W0c 0b R All 0s The peripheral supports all detectable errors except bits 29 and 26 The functional blocks involved for each detectable error condition are listed below along with a brief description of the capture register contents Logical Layer Error Detect CSR bit 31 LSU request packet is logged bit 30 TXU request packet is logged bit 29 Not supported bit 28 RXU request packet is logged bit...

Page 74: ...rect I O protocol When the single or multi packet data transfer is complete the external PE or the peripheral itself must notify the local processor that the data is available for processing To avoid erroneous data being processed by the local CPU the data transfer must complete through the DMA before the CPU interrupt is serviced This condition could occur since the data and interrupt queues are ...

Page 75: ...us with the write with response commands Interrupt pacing is also implemented at the peripheral level to manage the interrupt rate as described in Section 4 6 Error handling on the RapidIO link is handled by the peripheral and as such does not require the intervention of software for recovery This includes CRC errors due to bit rate errors that may cause erroneous or invalid operations The excepti...

Page 76: ... ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read W Write n value at reset Where ICS0 Doorbell0 bit 0 through ICS15 Doorbell0 bit 15 Figure 44 DOORBELL1 Interrupt Registers for Direct I O Transfers DOORBELL1 Interrupt Condition Status Registers ICSR Address Offset 0x0210 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 77: ... W 0 W 0 W 0 LEGEND R Read W Write n value at reset Where ICS0 Doorbell2 bit 0 through ICS15 Doorbell2 bit 15 Figure 46 DOORBELL3 Interrupt Registers for Direct I O Transfers DOORBELL3 Interrupt Condition Status Registers ICSR Address Offset 0x0230 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0 R W 0 R ...

Page 78: ...queue 15 Clearing of any ICSR bit depends on the CPU writing the value of last buffer descriptor processed to the RX DMA State CP Port hardware clears the ICSR bit only if the CP value written by the CPU equals the port written value in the RX DMA State CP register Figure 48 TX _CPPI Interrupts Using Messaging Mode Data Transfers TX_CPPI Interrupt Condition Status Registers ICSR Address Offset 0x0...

Page 79: ... 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read W Write n value at reset Where Bit 0 Transaction complete No Errors Posted Non posted LSU1 see note Bit 1 Non posted transaction received ERROR response or error in response payload LSU1 Bit 2 Transaction was not sent due to Xoff condition LSU1 Bit 3 Transaction was not sent due to unsupported transaction type or invalid field encoding LSU1 Bit 4 Transactio...

Page 80: ... the Load Store command registers This allows enabling disabling on a per request basis For optimum LSU performance interrupt pacing should not be used on the LSU interrupts Section 4 6 describes interrupt pacing Figure 50 ERR_RST_EVNT Error Reset and Special Event Interrupt ERR_RST_EVNT Interrupt Condition Status Registers ICSR Address Offset 0x0270 31 17 16 Reserved ICS16 R 0 R W 0 15 12 11 10 9...

Page 81: ...INTDST5 0110b Routed to INTDST6 0111b Routed to INTDST7 1111b No interrupt destination interrupt source disabled other Reserved Figure 51 Doorbell 0 Interrupt Condition Routing Registers DOORBELL0_ICRR Address Offset 0x280 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R Read W Write ...

Page 82: ...1 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R Read W Write n value at reset LSU_ICRR2 Address Offset 0x02E8 31 28 27 24 23 20 19 16 ICR23 ICR22 ICR21 ICR20 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR19 ICR18 ICR17 ICR16 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R Read W Write n value at reset LSU_ICRR3 Address Offset 0x02EC 31 28 27 24 23 20 19 16 I...

Page 83: ... Doorbell2 interrupts 0x0230 Doorbell3 interrupts 0x0240 Rx CPPI interrupts 0x0250 Tx CPPI interrupts 0x0260 LSU interrupts 0x0270 Error Reset and Special Event interrupts To reduce the number of reads up to 5 reads required to find the source bit an Interrupt Status Decode Register ISDR is implemented for each supported physical interrupt INTDST0 INTDST7 These registers are shown in Figure 56 Int...

Page 84: ...T1 INTDST2 INTDST3 INTDST4 INTDST5 INTDST6 INTDST7 TX CPPI ICRR TX CPPI ICRR TX CPPI ICSR RX CPPI ICSR 2 2 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Interrupt Conditions Figure 54 Sharing of ISDR Bits As an example if bit 29 of the ISDR is set this indicates that there is a pending interrupt on either the TX CPPI queue 2 or RX CPPI queue 2 Figure 55 illustrates the decode routing Figure 55 Example Diagram o...

Page 85: ...set only when the total number of set ICSR bits transitions from none to one or more The peripheral is responsible for setting the correct bit within the ICSR The ICRR register maps the pending interrupt request to the appropriate physical interrupt line The corresponding CPU is interrupted and reads the ISDR and ICSR registers to determine the interrupt source and appropriate action Interrupt gen...

Page 86: ...ffer for each core The correct circular buffer to read from and increment depends on the bit set in the ICSR register The CPU then clears the status bit For Error Status interrupts the peripheral must indicate to all the CPUs that one of the link ports has reached the error threshold In this case the peripheral sets the status bit indicating degraded or failed limits have been reached and an inter...

Page 87: ...ST_EVNT_ICCR SRIO_REGS DOORBELL0_ICCR 0xFFFFFFFF SRIO_REGS DOORBELL1_ICCR 0xFFFFFFFF SRIO_REGS DOORBELL2_ICCR 0xFFFFFFFF SRIO_REGS DOORBELL3_ICCR 0xFFFFFFFF SRIO_REGS INTDST0_Rate_CNTL 1 SRIO_REGS LSU_ICCR 0xFFFF SRIO_REGS INTDST1_Rate_CNTL 1 SPRU976 March 2006 Serial RapidIO SRIO 87 Submit Documentation Feedback ...

Page 88: ...6C BLK6_EN_STAT Block Enable Status 6 Section 5 8 0x0070 BLK7_EN Block Enable 7 Section 5 7 0x0074 BLK7_EN_STAT Block Enable Status 7 Section 5 8 0x0078 BLK8_EN Block Enable 8 Section 5 7 0x007C BLK8_EN_STAT Block Enable Status 8 Section 5 8 0x0080 DEVICEID_REG1 RapidIO DEVICEID1 Register Section 5 9 0x0084 DEVICEID_REG2 RapidIO DEVICEID2 Register Section 5 10 0x0090 PF_16B_CNTL0 Packet Forwarding...

Page 89: ...I Interrupt Clear Register Section 5 21 0x0260 LSU_ICSR LSU Interrupt Status Register Section 5 22 0x0268 LSU _ICCR LSU Interrupt Clear Register Section 5 23 0x0270 ERR_RST_EVNT_IC Error Reset and Special Event Interrupt Status Register Section 5 24 SR 0x0278 ERR_RST_EVNT_IC Error Reset and Special Event Interrupt Clear Register Section 5 25 CR 0x0280 DOORBELL0_ICRR DOORBELL0 Interrupt Condition R...

Page 90: ..._CN INTDST Interrupt Rate Control Register 2 Section 5 40 TL 0x032C INTDST3_RATE_CN INTDST Interrupt Rate Control Register 3 Section 5 40 TL 0x0330 INTDST4_RATE_CN INTDST Interrupt Rate Control Register 4 Section 5 40 TL 0x0334 INTDST5_RATE_CN INTDST Interrupt Rate Control Register 5 Section 5 40 TL 0x0338 INTDST6_RATE_CN INTDST Interrupt Rate Control Register 6 Section 5 40 TL 0x033C INTDST7_RATE...

Page 91: ...MA Head Descriptor Pointer Register 2 Section 5 49 DP 0x050C QUEUE3_TXDMA_H Queue Transmit DMA Head Descriptor Pointer Register 3 Section 5 49 DP 0x0510 QUEUE4_TXDMA_H Queue Transmit DMA Head Descriptor Pointer Register 4 Section 5 49 DP 0x0514 QUEUE5_TXDMA_H Queue Transmit DMA Head Descriptor Pointer Register 5 Section 5 49 DP 0x0518 QUEUE6_TXDMA_H Queue Transmit DMA Head Descriptor Pointer Regis...

Page 92: ... DMA Completion Pointer Register 13 Section 5 50 CP 0x05B8 QUEUE14_TXDMA_ Queue Transmit DMA Completion Pointer Register 14 Section 5 50 CP 0x05BC QUEUE15_TXDMA_ Queue Transmit DMA Completion Pointer Register 15 Section 5 50 CP 0x0600 QUEUE0_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 0 Section 5 51 DP 0x0604 QUEUE1_RXDMA_H Queue Receive DMA Head Descriptor Pointer Register 1 Sectio...

Page 93: ...ion 5 52 P 0x06A0 QUEUE8_RXDMA_C Queue Receive DMA Completion Pointer Register 8 Section 5 52 P 0x06A4 QUEUE9_RXDMA_C Queue Receive DMA Completion Pointer Register 9 Section 5 52 P 0x06A8 QUEUE10_RXDMA_ Queue Receive DMA Completion Pointer Register 10 Section 5 52 CP 0x06AC QUEUE11_RXDMA_ Queue Receive DMA Completion Pointer Register 11 Section 5 52 CP 0x06B0 QUEUE12_RXDMA_ Queue Receive DMA Compl...

Page 94: ...Mapping Register H5 Section 5 62 0x0830 RXU_MAP_L6 MailBox to Queue Mapping Register L6 Section 5 61 0x0834 RXU_MAP_H6 MailBox to Queue Mapping Register H6 Section 5 62 0x0838 RXU_MAP_L7 MailBox to Queue Mapping Register L7 Section 5 61 0x083C RXU_MAP_H7 MailBox to Queue Mapping Register H7 Section 5 62 0x0840 RXU_MAP_L8 MailBox to Queue Mapping Register L8 Section 5 61 0x0844 RXU_MAP_H8 MailBox t...

Page 95: ...gister L28 Section 5 61 0x08E4 RXU_MAP_H28 MailBox to Queue Mapping Register H28 Section 5 62 0x08E8 RXU_MAP_L29 MailBox to Queue Mapping Register L29 Section 5 61 0x08EC RXU_MAP_H29 MailBox to Queue Mapping Register H29 Section 5 62 0x08F0 RXU_MAP_L30 MailBox to Queue Mapping Register L30 Section 5 61 0x08F4 RXU_MAP_H30 MailBox to Queue Mapping Register H30 Section 5 62 0x08F8 RXU_MAP_L31 MailBox...

Page 96: ...n 5 81 0x1164 SP1_LM_RESP Port 1 Link Maintenance Response CSR Section 5 82 0x1168 SP1_ACKID_STAT Port 1 Local AckID Status CSR Section 5 83 0x1178 SP1_ERR_STAT Port 1 Error and Status CSR Section 5 84 0x117C SP1_CTL Port 1 Control CSR Section 5 85 0x1180 SP2_LM_REQ Port 2 Link Maintenance Request CSR Section 5 81 0x1184 SP2_LM_RESP Port 2 Link Maintenance Response CSR Section 5 82 0x1188 SP2_ACKI...

Page 97: ... 100 G4 0x20A8 SP1_ERR_RATE Port 1 Error Rate CSR Section 5 101 0x20AC SP1_ERR_THRESH Port 1 Error Rate Threshold CSR Section 5 102 0x20C0 SP2_ERR_DET Port 2 Error Detect CSR Section 5 94 0x20C4 SP2_RATE_EN Port 2 Error Enable CSR Section 5 95 0x20C8 SP2_ERR_ATTR_CA Port 2 Attributes Error Capture CSR 0 Section 5 96 PT_DBG0 0x20CC SP2_ERR_CAPT_DB Port 2 Packet Control Symbol Error Capture CSR 1 Se...

Page 98: ...4014 SP0_CS_TX Port 0 Control Symbol Transmit Register Section 5 111 0x14100 SP1_RST_OPT Port 1 Reset Option CSR Section 5 107 0x14104 SP1_CTL_INDEP Port 1 Control Independent Register Section 5 108 0x14108 SP1_SILENCE_TIME Port 1 Silence Timer Register Section 5 109 R 0x1410C SP1_MULT_EVNT_C Port 1 Multicast Event Control Symbol Request Register Section 5 110 S 0x14114 SP1_CS_TX Port 1 Control Sy...

Page 99: ...set state Figure 58 Peripheral ID Register PID 31 24 23 16 Reserved TYPE R 0x00 R 0x01 LEGEND R Read only n value after reset 15 8 7 0 CLASS REV R 0x0A R 0x01 LEGEND R Read only n value after reset Table 29 Peripheral ID Register PID Field Descriptions Bit Field Value Description 31 24 Reserved Reserved 23 16 TYPE Peripheral type Identifies the type of the peripheral RIO 15 8 CLASS Peripheral clas...

Page 100: ...alue after reset 15 3 2 1 0 Reserved PERE SOFT FREE N R 0x00 RW RW RW 0x00 0x00 0x01 LEGEND R Read only n value after reset Table 30 Peripheral Control Register PCR Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 PEREN Peripheral Enable Controls the flow of data in the logical layer of the peripheral As an initiator it will prevent TX transaction generation and as a target ...

Page 101: ... not put in sleep mode while in shutdown 25 LOOPBACK Loopback mode 0b Normal operation 1b Loop back mode Transmit data to receive on the same port Packet data is looped back in the digital domain before the SERDES macros 24 BOOT_COMPLE Controls ability to write any register during initialization It also includes read only registers during TE normal mode of operation that have application defined r...

Page 102: ...equency prescaler used to drive the request to response timers These 4 bits are the LECT prescaler reload value allowing division of the DMA clock by a range from 1 up to 16 Setting should reflect the device DMA frequency 0000b Sets the internal clock frequency Min 44 7 and Max 89 5 0001b Sets the internal clock frequency Min 89 5 and Max 179 0 0010b Sets the internal clock frequency Min 134 2 and...

Page 103: ... Drives SERDES Macro 3 PLL Enable signal 0b Disables macro 3 PLL 1b Enables macro 3 PLL 1 ENPLL2 Drives SERDES Macro 2 PLL Enable signal 0b Disables macro 2 PLL 1b Enables macro 2 PLL 0 ENPLL1 Drives SERDES Macro 1 PLL Enable signal 0b Disables macro 1 PLL 1b Enables macro 1 PLL SPRU976 March 2006 Serial RapidIO SRIO 103 Submit Documentation Feedback ...

Page 104: ... EN R 0x00 RW 0x00 LEGEND R Read only n value after reset Table 32 Peripheral Global Enable Register GBL_EN Field Descriptions Bit Field Value Description 31 1 Reserved Reserved 0 EN Controls reset to all clock domains within the peripheral 0b Peripheral to be disabled held in reset clocks disabled 1b Peripheral to be enabled Serial RapidIO SRIO 104 SPRU976 March 2006 Submit Documentation Feedback...

Page 105: ...eserved GBL_ EN_S TAT R 0x00 R Undefi ned LEGEND R Read only n value after reset Table 33 Peripheral Global Enable Status Register GBL_EN_STAT Field Descriptions Bit Field Value Description 31 1 Reserved Reserved 0 GBL_EN_STAT Indicates state of GBL_EN reset signal 0 Peripheral in reset and all clocks are off 1 Peripheral enabled and clocking SPRU976 March 2006 Serial RapidIO SRIO 105 Submit Docum...

Page 106: ...d only n value after reset 15 1 0 Reserved EN R 0x00 RW Undefi ned LEGEND R Read only n value after reset Table 34 Block n Enable Register BLKn_EN Field Descriptions Bit Field Value Description 31 1 Reserved Reserved 0 EN Controls reset to nth 0 to 8 clock logical domain 0 Logical block n disabled held in reset clocks disabled 1 Logical block n enabled Serial RapidIO SRIO 106 SPRU976 March 2006 Su...

Page 107: ...ead only n value after reset 15 1 0 Reserved EN_S TAT R 0x00 R Undefi ned LEGEND R Read only n value after reset Table 35 Block n Enable Status Register BLKn_EN_STAT Field Descriptions Bit Field Value Description 31 1 Reserved Reserved 0 EN_STAT Indicates state of BLKn_EN reset signal 0 Logical block n disabled in reset and clock is off 1 Logical block n enabled and clocking SPRU976 March 2006 Ser...

Page 108: ... Descriptions Bit Field Value Description 31 24 Reserved Reserved 23 16 8BNODEID This value is equal to the value of the RapidIO Base Device ID CSR The CPU must read the CSR value and set this register so that outgoing packets contain the correct SOURCEID value 15 0 16BNODEID This value is equal to the value of the RapidIO Base Device ID CSR The CPU must read the CSR value and set this register so...

Page 109: ...Table 37 RapidIO DEVICEID2 Register DEVICEID_REG2 Field Descriptions Bit Field Value Description 31 24 Reserved Reserved 23 16 8BNODEID This is a secondary supported DeviceID checked against an incoming packet s DestID field Typically used for Multi cast support 15 0 16BNODEID This is a secondary supported DeviceID checked against an incoming packet s DestID field Typically used for Multi cast sup...

Page 110: ...eset 15 0 16BIT_DEVID_LOW_BOUND RW 0xFFFF LEGEND R Read only n value after reset Table 38 Packet Forwarding Register n for 16b DeviceIDs PF_16B_CNTLn Field Descriptions Bit Field Value Description 31 16 16BIT_DEVID_U Upper 16b DeviceID boundary DestID above this range cannot use the table entry P_BOUND 15 0 16BIT_DEVID_L Lower 16b DeviceID boundary DestID lower than this number cannot use the tabl...

Page 111: ... R Read only n value after reset Table 39 Packet Forwarding Register n for 8b DeviceIDs PF_8B_CNTLn Field Descriptions Bit Field Value Description 31 18 Reserved Reserved 17 16 OUT_BOUND_P Output port number for packets whose DestID falls within the 8b or 16b range for this table entry ORT 15 8 8BIT_DEVID_UP Upper 8b DeviceID boundary DestID above this range cannot use the table entry _BOUND 7 0 8...

Page 112: ...changes in frequency offset and fastest lock time but lowest precision frequency offset matching Suitable for use in systems with spread spectrum clocking 100 First order with fast lock Phase offset tracking up to 1953 ppm in the presence of 10101010 training pattern and 448 ppm otherwise 101 Second order with fast lock As per setting 001 but with improved response to changes in frequency offset w...

Page 113: ...7 INVPAIR Invert polarity Inverts polarity of RXPI and RXNn 0 Normal polarity RXPn considered to be positive data and RXNi negative 1 Inverted polarity RXPn considered to be negative data and RXNn positive 6 5 RATE Operating rate Selects full half or quarter rate operation 00 Full rate Two data samples taken per PLL output clock cycle 01 Half rate One data sample taken per PLL output clock cycle 1...

Page 114: ... one of 8 outputs amplitude settings between 125 and 1250mVdfpp See Table 43 8 CM Common mode Adjusts the common mode to suit the termination at the attached receiver 0 Normal common mode Common mode not adjusted 1 Raised common mode Common mode raised by 5 of e54 7 INVPAIR Invert polarity Inverts polarity of TXPn and TXNn 0 Normal polarity TXPn considered to be positive data and TXNn negative 1 I...

Page 115: ...ts CFGTX 15 12 Amplitude Reduction dB 0000 0 0 0001 4 76 0 42 0010 9 52 0 87 0011 14 28 1 34 0100 19 04 1 83 0101 23 8 2 36 0110 28 56 2 92 0111 33 32 3 52 1000 38 08 4 16 1001 42 85 4 86 1010 47 61 5 61 1011 52 38 6 44 1100 57 14 7 35 1101 61 9 8 38 1110 66 66 9 54 1111 71 42 10 87 SPRU976 March 2006 Serial RapidIO SRIO 115 Submit Documentation Feedback ...

Page 116: ...ify loop bandwidth settings 00 Frequency dependent bandwidth The PLL bandwidth is set to a twelfth of the frequency of RIOCLK RIOCLK 01 Reserved 10 Low bandwidth The PLL bandwidth is set to a twentieth of the frequency of RIOCLK RIOCLK or 3MHz whichever is larger 11 High bandwidth The PLL bandwidth is set to a eighth of the frequency of RIOCLK RIOCLK 7 6 Reserved Reserved 5 1 MPY PLL multiply Sele...

Page 117: ...RBELLn_ICSR 31 16 Reserved R 0x00 LEGEND R Read only n value after reset 15 0 ICS 0 15 R 0x00 LEGEND R Read only n value after reset Table 46 DOORBELLn Interrupt Status Register DOORBELLn_ICSR Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 ICS 0 15 Doorbell n 0 to 3 interrupt condition status bits SPRU976 March 2006 Serial RapidIO SRIO 117 Submit Documentation Feedback...

Page 118: ...r DOORBELLn_ICCR 31 16 Reserved R 0x00 LEGEND R Read only n value after reset 15 0 ICC 0 15 W 0x00 LEGEND R Read only n value after reset Table 47 DOORBELLn Interrupt Clear Register DOORBELLn_ICCR Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 ICC 0 15 Doorbell n 0 to 3 interrupt clear bits Serial RapidIO SRIO 118 SPRU976 March 2006 Submit Documentation Feedback ...

Page 119: ...GEND R Read only n value after reset 15 0 ICS 0 15 R 0x00 LEGEND R Read only n value after reset Table 48 RX CPPI Interrupt Status Register RX_CPPI_ICSR Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 ICS 0 15 RX CPPI Interrupt Buffer descriptor Queue 0 to 15 SPRU976 March 2006 Serial RapidIO SRIO 119 Submit Documentation Feedback ...

Page 120: ...D R Read only n value after reset 15 0 ICC 0 15 W 0x00 LEGEND R Read only n value after reset Table 49 RX CPPI Interrupt Clear Register RX_CPPI_ICCR Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 ICC 0 15 RX CPPI Interrupt clear Buffer descriptor Queue 0 to 15 Serial RapidIO SRIO 120 SPRU976 March 2006 Submit Documentation Feedback ...

Page 121: ...GEND R Read only n value after reset 15 0 ICS 0 15 R 0x00 LEGEND R Read only n value after reset Table 50 TX CPPI Interrupt Status Register TX_CPPI_ICSR Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 ICS 0 15 TX CPPI Interrupt Buffer descriptor Queue 0 to 15 SPRU976 March 2006 Serial RapidIO SRIO 121 Submit Documentation Feedback ...

Page 122: ...D R Read only n value after reset 15 0 ICC 0 15 W 0x00 LEGEND R Read only n value after reset Table 51 TX CPPI Interrupt Clear Register TX_CPPI_ICCR Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 ICC 0 15 TX CPPI Interrupt clear Buffer descriptor Queue 0 to 15 Serial RapidIO SRIO 122 SPRU976 March 2006 Submit Documentation Feedback ...

Page 123: ...R 0x00 LEGEND R Read only n value after reset 15 0 ICS 15 0 R 0x00 LEGEND R Read only n value after reset Table 52 LSU Status Interrupt Register LSU_ICSR Field Descriptions Bit Field Value Description 31 0 ICS 31 0 Load Store module interrupt condition status bits SPRU976 March 2006 Serial RapidIO SRIO 123 Submit Documentation Feedback ...

Page 124: ...1 16 W 0x00 LEGEND R Read only n value after reset 15 0 ICC 15 0 W 0x00 LEGEND R Read only n value after reset Table 53 LSU Clear Interrupt Register LSU _ICCR Field Descriptions Bit Field Value Description 31 0 ICS 31 0 Load Store module interrupt clear bits Serial RapidIO SRIO 124 SPRU976 March 2006 Submit Documentation Feedback ...

Page 125: ...x00 0x00 LEGEND R Read only n value after reset Table 54 Error Reset and Special Event Status Interrupt Register ERR_RST_EVNT_ICSR Field Descriptions Bit Field Value Description 31 17 Reserved Reserved 16 ICS16 Device Reset Interrupt from any port 15 12 Reserved Reserved 11 ICS11 Port3 Error 10 ICS10 Port2 Error 9 ICS9 Port1 Error 8 ICS8 Port0 Error 7 3 Reserved Reserved 2 ICS2 Logical Layer Error...

Page 126: ... LEGEND R Read only n value after reset Table 55 Error Reset and Special Event Clear Interrupt Register ERR_RST_EVNT_ICCR Field Descriptions Bit Field Value Description 31 17 Reserved Reserved 16 ICC16 Device Reset Interrupt from any port 15 12 Reserved Reserved 11 ICC11 Port3 Error 10 ICC10 Port2 Error 9 ICC9 Port1 Error 8 ICC8 Port0 Error 7 3 Reserved Reserved 2 ICC2 Logical Layer Error Manageme...

Page 127: ... 20 19 16 ICR7 ICR6 ICR5 ICR4 R W 0x00 R W 0x00 R W 0x00 R W 0x00 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R W 0x00 R W 0x00 R W 0x00 R W 0x00 LEGEND R Read W Write n value at reset Table 56 DOORBELLn Interrupt Condition Routing Register DOORBELLn_ICRR Field Descriptions Bit Field Value Description 31 0 ICR 0 7 Doorbell n 0 to 3 CPU servicing interrupt condition routing bits SPRU976 March 2006 Seria...

Page 128: ...0 19 16 ICR15 ICR14 ICR13 ICR12 R W 0x00 R W 0x00 R W 0x00 R W 0x00 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0x00 R W 0x00 R W 0x00 R W 0x00 LEGEND R Read W Write n value at reset Table 57 DOORBELLn Interrupt Condition Routing Register 2 DOORBELLn_ICRR2 Field Descriptions Bit Field Value Description 31 0 ICR 8 15 Doorbell n 0 to 3 CPU servicing interrupt condition routing bits Serial RapidIO S...

Page 129: ...5 ICR4 R W 0x00 R W 0x00 R W 0x00 R W 0x00 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R W 0x00 R W 0x00 R W 0x00 R W 0x00 LEGEND R Read W Write n value at reset Table 58 RX CPPI Interrupt Condition Routing Register RX_CPPI _ICRR Field Descriptions Bit Field Value Description 31 0 ICR 0 7 RX CPPI Interrupt condition routing bits SPRU976 March 2006 Serial RapidIO SRIO 129 Submit Documentation Feedback ...

Page 130: ...0 ICR11 ICR10 ICR9 ICR8 R W 0x00 R W 0x00 R W 0x00 R W 0x00 LEGEND R Read W Write n value at reset 31 16 ICR 0 7 RW 0x00 LEGEND R Read only n value after reset 15 0 ICR 0 7 RW 0x00 LEGEND R Read only n value after reset Table 59 RX CPPI Interrupt Condition Routing Register RX_CPPI _ICRR2 Field Descriptions Bit Field Value Description 31 0 ICR 8 15 RX CPPI Interrupt condition routing bits Serial Ra...

Page 131: ...5 ICR4 R W 0x00 R W 0x00 R W 0x00 R W 0x00 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R W 0x00 R W 0x00 R W 0x00 R W 0x00 LEGEND R Read W Write n value at reset Table 60 TX CPPI Interrupt Condition Routing Register TX_CPPI _ICRR Field Descriptions Bit Field Value Description 31 0 ICR 0 7 TX CPPI Interrupt condition routing bits SPRU976 March 2006 Serial RapidIO SRIO 131 Submit Documentation Feedback ...

Page 132: ...3 ICR12 R W 0x00 R W 0x00 R W 0x00 R W 0x00 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0x00 R W 0x00 R W 0x00 R W 0x00 LEGEND R Read W Write n value at reset Table 61 TX CPPI Interrupt Condition Routing Register TX_CPPI _ICRR2 Field Descriptions Bit Field Value Description 31 0 ICR 8 15 TX CPPI Interrupt condition routing bits Serial RapidIO SRIO 132 SPRU976 March 2006 Submit Documentation Feedb...

Page 133: ...4 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R Read W Write n value at reset Table 62 LSU Module Interrupt Condition Routing Register 0 LSU_ICRR0 Field Descriptions Bit Field Value Description 31 0 ICR 7 0 Load Store module interrupt condition routing bits SPRU976 March 2006 Serial RapidIO SRIO 133 Submit Documentation Feed...

Page 134: ...12 R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R Read W Write n value at reset Table 63 LSU Module Interrupt Condition Routing Register 1 LSU_ICRR1 Field Descriptions Bit Field Value Description 31 0 ICR 15 8 Load Store module interrupt condition routing bits Serial RapidIO SRIO 134 SPRU976 March 2006 Submit Documentation ...

Page 135: ... R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR19 ICR18 ICR17 ICR16 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R Read W Write n value at reset Table 64 LSU Module Interrupt Condition Routing Register 2 LSU_ICRR2 Field Descriptions Bit Field Value Description 31 0 ICR 23 16 Load Store module interrupt condition routing bits SPRU976 March 2006 Serial RapidIO SRIO 135 Submit Documentation...

Page 136: ... R W 0000 R W 0000 R W 0000 R W 0000 15 12 11 8 7 4 3 0 ICR27 ICR26 ICR25 ICR24 R W 0000 R W 0000 R W 0000 R W 0000 LEGEND R Read W Write n value at reset Table 65 LSU Module Interrupt Condition Routing Register 3 LSU_ICRR3 Field Descriptions Bit Field Value Description 31 0 ICR 31 24 Load Store module interrupt condition routing bits Serial RapidIO SRIO 136 SPRU976 March 2006 Submit Documentation...

Page 137: ...R 0x00 RW 0x00 RW 0x00 RW 0x00 LEGEND R Read only n value after reset Table 66 Error Reset and Special Event Interrupt Condition Routing Register ERR_RST_EVNT_ICRR Field Descriptions Bit Field Value Description 31 12 Reserved Reserved 11 8 ICR2 Logical Layer Error Management Event Capture routing 7 4 ICR1 Routing of Port write in request received on any port 3 0 ICR0 Routing of Multi cast event co...

Page 138: ...et 15 12 11 8 7 4 3 0 ICR11 ICR10 ICR9 ICR8 RW 0x00 RW 0x00 RW 0x00 RW 0x00 LEGEND R Read only n value after reset Table 67 Error Reset and Special Event Interrupt Condition Routing Register 2 ERR_RST_EVNT_ICRR2 Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 12 ICR11 Port3 Error routing 11 8 ICR10 Port2 Error routing 7 4 ICR9 Port1 Error routing 3 0 ICR8 Port0 Error rout...

Page 139: ...erved R 0x00 LEGEND R Read only n value after reset 15 4 3 0 Reserved ICR16 R 0x00 RW 0x00 LEGEND R Read only n value after reset Table 68 Error Reset and Special Event Interrupt Condition Routing Register 3 ERR_RST_EVNT_ICRR3 Field Descriptions Bit Field Value Description 31 4 Reserved Reserved 3 0 ICR16 Routing of Device Reset Interrupt from any port SPRU976 March 2006 Serial RapidIO SRIO 139 Su...

Page 140: ...tatus Decode Registers INTDSTn_DECODE Field Descriptions Bit Field Value Description 31 0 ISDRn Interrupt sources that select a particular physical interrupt destination are mapped to specific bits in the decode register The interrupt sources are mapped to an interrupt decode register only if the ICRR routes the interrupt source to the corresponding physical interrupt The status decode bit is a lo...

Page 141: ...N_ The rate at which an interrupt can be generated is controllable for each physical interrupt VALUE destination Rate control is implemented with a programmable down counter The counter reloads and immediately starts down counting each time the CPU writes these registers Once the rate control counter register is written and the counter value reaches zero note the CPU may write zero immediately for...

Page 142: ...r 0 LSUn_REG0 31 16 ADDRESS_MSB RW 0x00 LEGEND R Read only n value after reset 15 0 ADDRESS_MSB RW 0x00 LEGEND R Read only n value after reset Table 71 LSUn Control Register 0 LSUn_REG0 Field Descriptions Bit Field Value Description 31 0 ADDRESS_MSB 32 bit Ext address fields Serial RapidIO SRIO 142 SPRU976 March 2006 Submit Documentation Feedback ...

Page 143: ...gister 1 LSUn_REG1 Field Descriptions Bit Field Value Description 31 0 ADDRESS_LSB_ 1 32b Address Packet Types 2 5 and 6 will be used in conjunction with BYTE_COUNT to CONFIG_OFFSE create 64b aligned RapidIO packet header address T 2 24b Config offset Field Maintenance Packets Type 8 will be used in conjunction with BYTE_COUNT to create 64b aligned RapidIO packet header Config_offset The 2 lsb of ...

Page 144: ...ter 2 LSUn_REG2 31 16 DSP_ADDRESS RW 0x00 LEGEND R Read only n value after reset 15 0 DSP_ADDRESS RW 0x00 LEGEND R Read only n value after reset Table 73 LSUn Control Register 2 LSUn_REG2 Field Descriptions Bit Field Value Description 31 0 DSP_ADDRESS 32b DSP byte address Serial RapidIO SRIO 144 SPRU976 March 2006 Submit Documentation Feedback ...

Page 145: ...2 11 0 Reserved BYTE_COUNT R 0x00 RW 0x00 LEGEND R Read only n value after reset Table 74 LSUn Control Register 3 LSUn_REG3 Field Descriptions Bit Field Value Description 31 12 Reserved Reserved 11 0 BYTE_COUNT Number of data bytes to Read Write up to 4KB Used in conjunction with RapidIO address to create WRSIZE RDSIZE and WDPTR in RapidIO packet header SPRU976 March 2006 Serial RapidIO SRIO 145 S...

Page 146: ...29 28 PRIORITY RapidIO prio field specifying packet priority Request packets should not be sent at a priority level of 3 in order to avoid system deadlock It is the responsibility of the software to assign the appropriate outgoing priority 27 26 XAMBS RapidIO xambs field specifying extended address MSB 25 24 ID_SIZE RapidIO tt field specifying 8 or 16bit DeviceIDs 00b 8 bit device Ids 01b 16 bit d...

Page 147: ...0x00 RW 0x00 LEGEND R Read only n value after reset Table 76 LSUn Control Register 5 LSUn_REG5 Field Descriptions Bit Field Value Description 31 16 DRBLL_INFO RapidIO doorbell info field for type 10 packets 15 8 HOP_COUNT RapidIO HOP_COUNT field specified for Type 8 Maintenance packets 7 0 PACKET_TYPE 4 msb 4b ftype field for all packets and 4 lsb 4b trans field for Packet types 2 5 8 SPRU976 Marc...

Page 148: ... Transaction complete Packet not sent due to flow control blockade Xoff 011b Transaction complete Non posted response packet type 8 and 13 contained ERROR status or response payload length was in error 100b Transaction complete Packet not sent due to unsupported transaction type or invalid programming encoding for one or more LSU register fields 101b DMA data transfer error 110b Retry DOORBELL res...

Page 149: ...rved R 0x00 LEGEND R Read only n value after reset 15 0 FLOW_MASK 0 15 RW 0x01 LEGEND R Read only n value after reset Table 78 LSU Congestion Control Flow Mask n LSU_FLOW_MASKS n Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 FLOW_MASK LSU flow masks 0 15 SPRU976 March 2006 Serial RapidIO SRIO 149 Submit Documentation Feedback ...

Page 150: ...MA Head Descriptor Pointer Registers QUEUEn_TXDMA_HDP Field Descriptions Bit Field Value Description 31 0 TX_HDP This field is the host memory address for the first buffer descriptor in the transmit queue This field is written by the host to initiate queue transmit operations and is zeroed by the port when all packets in the queue have been transmitted An error condition results if the host writes...

Page 151: ...er reset Table 80 Queue Transmit DMA Completion Pointer Registers QUEUEn_TXDMA_CP Field Descriptions Bit Field Value Description 31 0 TX_CP This field is the host memory address for the transmit queue completion pointer This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to det...

Page 152: ...iptor Pointer Registers QUEUEn_RXDMA_HDP Field Descriptions Bit Field Value Description 31 0 RX_HDP Rx Queue Head Descriptor Pointer This field is the host memory address for the first buffer descriptor in the channel receive queue This field is written by the host to initiate queue receive operations and is zeroed by the port when all free buffers have been used An error condition results if the ...

Page 153: ... 82 Queue Receive DMA Completion Pointer Registers QUEUEn_RXDMA_CP Field Descriptions Bit Field Value Description 31 0 RX_CP Rx Queue Completion Pointer This field is the host memory address for the receive queue completion pointer This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value wr...

Page 154: ... TX_QUEUE_TEAR_DOWN Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 QUEUE15_TEAR Write 1 tear down of Queue 15 _DWN 14 QUEUE14_TEAR Write 1 tear down of Queue 14 _DWN 13 QUEUE13_TEAR Write 1 tear down of Queue 13 _DWN 12 QUEUE12_TEAR Write 1 tear down of Queue 12 _DWN 11 QUEUE11_TEAR Write 1 tear down of Queue 11 _DWN 10 QUEUE10_TEAR Write 1 tear down of Queue 10 _DWN 9 Q...

Page 155: ..._FLOW_MASKS2 31 16 15 0 QUEUE5_FLOW_MASK QUEUE4_FLOW_MASK RW 0x01 RW 0x01 LEGEND R Read only n value after reset Transmit CPPI Supported Flow Mask Register 3 TX_CPPI_FLOW_MASKS3 31 16 15 0 QUEUE7_FLOW_MASK QUEUE6_FLOW_MASK RW 0x01 RW 0x01 LEGEND R Read only n value after reset Transmit CPPI Supported Flow Mask Register 4 TX_CPPI_FLOW_MASKS4 31 16 15 0 QUEUE9_FLOW_MASK QUEUE8_FLOW_MASK RW 0x01 RW 0...

Page 156: ...ue after reset Table 84 Transmit CPPI Supported Flow Mask Registers n TX_CPPI_FLOW_MASKSn Field Descriptions Field Value Description QUEUEn_FLOW_ Flow mask queue n MASK 0b Transmit source does not support flow n from table entry for QUEUEn 1b Transmit source does support flow n from table entry for QUEUEn Serial RapidIO SRIO 156 SPRU976 March 2006 Submit Documentation Feedback ...

Page 157: ...X_QUEUE_TEAR_DOWN Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 QUEUE15_TEAR Write 1 tear down of Queue 15 _DWN 14 QUEUE14_TEAR Write 1 tear down of Queue 14 _DWN 13 QUEUE13_TEAR Write 1 tear down of Queue 13 _DWN 12 QUEUE12_TEAR Write 1 tear down of Queue 12 _DWN 11 QUEUE11_TEAR Write 1 tear down of Queue 11 _DWN 10 QUEUE10_TEAR Write 1 tear down of Queue 10 _DWN 9 QUE...

Page 158: ...ORD _ORD _ORD _ORD _ORD _ORD _ORD _ORD DER DER DER DER DER DER ER ER ER ER ER ER ER ER ER ER RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 LEGEND R Read only n value after reset Table 86 Receive CPPI Control Register RX_CPPI_CNTL Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 QUEUEn_IN_OR...

Page 159: ...n 31 28 TX_QUEUE_MAP Number of contiguous messages descriptors to process before moving to TX_Queue_Map4 3_NUM_MSGS 27 24 TX_QUEUE_MAP Pointer to a Queue programmable to any of the 16 TX queues 3_QUEUE_PTR 23 20 TX_QUEUE_MAP Number of contiguous messages descriptors to process before moving to TX_Queue_Map3 2_NUM_MSGS 19 16 TX_QUEUE_MAP Pointer to a Queue programmable to any of the 16 TX queues 2_...

Page 160: ...n 31 28 TX_QUEUE_MAP Number of contiguous messages descriptors to process before moving to TX_Queue_Map8 7_NUM_MSGS 27 24 TX_QUEUE_MAP Pointer to a Queue programmable to any of the 16 TX queues 7_QUEUE_PTR 23 20 TX_QUEUE_MAP Number of contiguous messages descriptors to process before moving to TX_Queue_Map7 6_NUM_MSGS 19 16 TX_QUEUE_MAP Pointer to a Queue programmable to any of the 16 TX queues 6_...

Page 161: ... 31 28 TX_QUEUE_MAP Number of contiguous messages descriptors to process before moving to TX_Queue_Map12 11_NUM_MSGS 27 24 TX_QUEUE_MAP Pointer to a Queue programmable to any of the 16 TX queues 11_QUEUE_PTR 23 20 TX_QUEUE_MAP Number of contiguous messages descriptors to process before moving to TX_Queue_Map11 10_NUM_MSGS 19 16 TX_QUEUE_MAP Pointer to a Queue programmable to any of the 16 TX queue...

Page 162: ... 31 28 TX_QUEUE_MAP Number of contiguous messages descriptors to process before moving to TX_Queue_Map0 15_NUM_MSGS 27 24 TX_QUEUE_MAP Pointer to a Queue programmable to any of the 16 TX queues 15_QUEUE_PTR 23 20 TX_QUEUE_MAP Number of contiguous messages descriptors to process before moving to TX_Queue_Map15 14_NUM_MSGS 19 16 TX_QUEUE_MAP Pointer to a Queue programmable to any of the 16 TX queues...

Page 163: ...mapping register 29 24 MAILBOX_MASK Allowed mail box mask for this mapping register 23 22 LETTER Allowed letter for this mapping register 21 16 MAILBOX Allowed mail box for this mapping register 15 0 SOURCEID The SOURCEID field is used to indicate which external device has access to the mapping entry and corresponding queue A compare is performed between the sourceID of the incoming message packet...

Page 164: ...ping Register Hn RXU_MAP_Hn Field Descriptions Bit Field Value Description 31 10 Reserved Reserved 9 8 TT Transport type 0b Matches the 8 LSB of the source ID 1b Matches the full 16 bits of the source ID 7 6 Reserved Reserved 5 2 QUEUE_ID Corresponding queue 0 to queue 15 1 PROMISCUOUS Promiscuous 1 full access to the queue for any source ID 0b Promiscuous bit enabled 1b Promiscuous bit disabled 0...

Page 165: ...ND R Read only n value after reset 15 0 FLOW_CNTL_ID RW 0x00 LEGEND R Read only n value after reset Table 93 Flow Control Table Entry Registers FLOW_CNTLn Field Descriptions Bit Field Value Description 31 18 Reserved Reserved 17 16 TT Selects Flow Cntl ID length 00b 8 bit Ids 01b 16 bit Ids 10b Reserved 11b 15 0 FLOW_CNTL_ID DestID of Flow n SPRU976 March 2006 Serial RapidIO SRIO 165 Submit Docume...

Page 166: ...15 0 DEVICE_VENDORIDENTITY R 0x0030 LEGEND R Read only n value after reset Table 94 Device Identity CAR DEV_ID Field Descriptions Bit Field Value Description 31 16 DEVICEIDENTIT Identifies the type of device Vendor specific Y 15 0 DEVICE_VENDO Device Vendor ID assigned by RapidIO TA RIDENTITY Serial RapidIO SRIO 166 SPRU976 March 2006 Submit Documentation Feedback ...

Page 167: ...REV R 0x0000 LEGEND R Read only n value after reset 15 0 DEVICEREV R 0x0000 LEGEND R Read only n value after reset Table 95 Device Information CAR DEV_INFO Field Descriptions Bit Field Value Description 31 0 DEVICEREV Vendor supply device revision SPRU976 March 2006 Serial RapidIO SRIO 167 Submit Documentation Feedback ...

Page 168: ...eset 15 0 ASSY_VENDORIDENTITY R 0x0030 LEGEND R Read only n value after reset Table 96 Assembly Identity CAR ASBLY_ID Field Descriptions Bit Field Value Description 31 16 ASSY_IDENTITY Assembly Identifier Vendor Specific 15 0 ASSY_VENDORI Assembly Vendor Identifier assigned by RapidIO TA DENTITY Serial RapidIO SRIO 168 SPRU976 March 2006 Submit Documentation Feedback ...

Page 169: ...e after reset 15 0 EXTENDEDFEATURESPTR R 0x0100 LEGEND R Read only n value after reset Table 97 Assembly Information CAR ASBLY_INFO Field Descriptions Bit Field Value Description 31 16 ASSYREV Assembly revision level 15 0 EXTENDEDFEAT Pointer to first entry in extended features list URESPTR SPRU976 March 2006 Serial RapidIO SRIO 169 Submit Documentation Feedback ...

Page 170: ...RapidIO interface an internal port to a local endpoint does not count as a switch port For example a device with two RapidIO ports and a local endpoint is a two port switch not a three port switch regardless of the internal architecture 27 8 Reserved Reserved 7 FLOW_CONTRO PE supports congestion flow control mechanism L_SUPPORT 0b PE does not support flow control 1b PE supports flow control 6 RETR...

Page 171: ... IMPLMNT_DEFIN Defined by the device implementation ED_2 15 READ PE can support a read operation 14 WRITE PE can support a write operation 13 STREAM_WRITE PE can support a streaming write operation 12 WRITE_WITH_R PE can support a write with response operation ESP 11 DATA_MESS PE can support a data message operation 10 DOORBELL PE can support a doorbell operation 9 Reserved Reserved 8 ATOMIC_TEST_...

Page 172: ...rved 17 16 IMPLMNT_DEFIN Defined by the device implementation ED_2 15 READ PE can support a read operation 14 WRITE PE can support a write operation 13 STREAM_WRITE PE can support a streaming write operation 12 WRITE_WITH_R PE can support a write with response operation ESP 11 DATA_MESS PE can support a data message operation 10 DOORBELL PE can support a doorbell operation 9 Reserved Reserved 8 AT...

Page 173: ...e after reset Table 101 Processing Element Logical Layer Control CSR PE_LL_CTL Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 0 EXTENDED_ADD Controls the number of address bits generated by the PE as a source and processed by the PE as RESSING_CONT the target of an operation All other encodings reserved ROL 100b PE supports 66 bit addresses 010b PE supports 50 bit addresse...

Page 174: ...EGEND R Read only n value after reset Table 102 Local Configuration Space Base Address 0 CSR LCL_CFG_HBAR Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 0 LCSBA For bits 30 to 15 Reserved for 34b addresses reserved for 50b addresses bits 66 51 of a 66b address For bits 14 to 0 Reserved for 34b addresses bits 50 36 of a 50b address bits 50 36 of a 66b address Serial RapidIO ...

Page 175: ...R 0x00 LEGEND R Read only n value after reset Table 103 Local Configuration Space Base Address 1 CSR LCL_CFG_BAR Field Descriptions Bit Field Value Description 31 0 LCSBA For bit 31 Reserved for 34b addresses bit 35 of a 50b address bit 35 of a 66b address For bits 30 to 0 Bits 34 3 of a 34b address bits 35 3 of a 50b address bits 35 3 of a 66b address SPRU976 March 2006 Serial RapidIO SRIO 175 Su...

Page 176: ...r reset Table 104 Base Device ID CSR BASE_ID Field Descriptions Bit Field Value Description 31 24 Reserved Reserved 23 16 BASE_DEVICEID This is the base ID of the device in small common transport system endpoints only 15 0 LARGE_BASE_D This is the base ID of the device in a large common transport system Only valid for endpoints and EVICEID if bit 4 of the PE_FEAT Register is set Serial RapidIO SRI...

Page 177: ...ock CSR HOST_BASE_ID_LOCK 31 16 Reserved R 0x00 LEGEND R Read only n value after reset 15 0 HOST_BASE_DEVICEID RW 0xFFFF LEGEND R Read only n value after reset Table 105 Host Base Device ID Lock CSR HOST_BASE_ID_LOCK Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 HOST_BASE_DE This is the base ID for the Host PE that is initializing this PE VICEID SPRU976 March 2006 Ser...

Page 178: ...ly n value after reset 15 0 COMPONENT_TAG RW 0x00 LEGEND R Read only n value after reset Table 106 Component Tag CSR COMP_TAG Field Descriptions Bit Field Value Description 31 0 COMPONENT_T Software defined component Tag for PE Useful for devices without device IDs AG Serial RapidIO SRIO 178 SPRU976 March 2006 Submit Documentation Feedback ...

Page 179: ...R Read only n value after reset Table 107 1x 4x LP_Serial Port Maintenance Block Header Register SP_MB_HEAD Field Descriptions Bit Field Value Description 31 16 EF_PTR Hard wired pointer to the next block in the data structure 15 0 EF_ID Hard wired extended features ID 0x0001 General endpoint device 0x0002 General endpoint device with software assisted error recovery option 0x0003 Switch SPRU976 M...

Page 180: ...e Description 31 8 TIMEOUT_VALU Timeout value for all ports on the device This timeout is for link events such as sending a packet to E receiving the corresponding ACK Max value represents 3 6 seconds Timeout duration 205nS Timeout Value where Timeout value is the decimal representation of this register value FFFFFF 3 4 seconds h 0FFFFF 215 ms h 00FFFF 13 4 ms h 000FFF 839 5 us h 0000FF 52 3 us h ...

Page 181: ...n 31 8 TIMEOUT_VALU Timeout value for all ports on the device This timeout is for sending a packet to receiving the E corresponding response packet Max value represents 3 6 seconds The timeout duration can be expressed as Timeout 15 Prescale value 1 DMA clock period Timeout Value where Prescale value is set in 0x0020 PSCR and the Timeout value is the decimal representation of this register value E...

Page 182: ...nance Agent or slave devices are typically initialized by Host devices 0b Agent or Slave device 1b Host device 30 MASTER_ENABL The Master Enable bit controls whether or not a device is allowed to issue requests into the system E If the Master Enable is not set the device may only respond to requests 0b Processing element cannot issue requests 1b Processing element can issue requests 29 DISCOVERED ...

Page 183: ... COMMAND R 0x00 RW 0x00 LEGEND R Read only n value after reset Table 111 Port Link Maintenance Request CSR n SPn_LM_REQ Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 0 COMMAND A write to this register generates a link request control symbol on the corresponding port interface Command to be sent in the link request control symbol If read this field returns the last written...

Page 184: ...nance Response CSR n SPn_LM_RESP Field Descriptions Bit Field Value Description 31 RESPONSE_VAL If the link request causes a link response this bit indicates that the link response has been ID received and the status fields are valid If the link request does not cause a link response this bit indicates that the link request has been transmitted This bit automatically clears on read 30 10 Reserved ...

Page 185: ...atus CSR n SPn_ACKID_STAT Field Descriptions Bit Field Value Description 31 29 Reserved Reserved 28 24 INBOUND_ACKI Input port next expected ackID value D 23 13 Reserved Reserved 12 8 OUTSTANDING_ Output port unacknowledged ackID status Next expected acknowledge control symbol ackID field ACKID that indicates the ackID value expected in the next received acknowledge control symbol 7 5 Reserved Res...

Page 186: ...T_RETRY Output port has encountered a retry condition This bit is set when bit 18 is set Once set remains _ENC set until written with a logic 1 to clear 19 OUTPUT_RETRI Output port has received a packet retry control symbol and can not make forward progress This bit ED is set when bit 18 is set and is cleared when a packet accepted or a packet not accepted control symbol is received read only 18 O...

Page 187: ...n 1 PORT_OK The input and output ports are initialized and the port is exchanging error free control symbols with the attached device read only 0 PORT_UNINITIA Input and output ports are not initialized This bit and bit 1 are mutually exclusive read only LIZED SPRU976 March 2006 Serial RapidIO SRIO 187 Submit Documentation Feedback ...

Page 188: ...valid for SP1 SP2 and SP3 00b Single lane port 01b Four lane port 10b 11b Reserved 29 27 INITIALIZED_PO Width of the ports after initialized read only RT_WIDTH 000b Single lane port lane 0 001b Single lane port lane 2 010b Four lane port 011b Reserved 111b 26 24 PORT_WIDTH_O Soft port configuration to override the hardware size VERRIDE 000b No override 001b Reserved 010b Force single lane lane 0 0...

Page 189: ...ting to send packets to the connected device when the Output Failed encountered bit is set Packets are discarded if the Drop Packet Enable bit is set When cleared the port continues to attempt to transmit packets to the connected device if the Output Failed encountered bit is set 2 DROP_PACKET_ When set this bit allows the output port to drop packets that are acknowledged with a ENABLE packet not ...

Page 190: ...e after reset 15 0 EF_ID R 0x0007 LEGEND R Read only n value after reset Table 116 Error Reporting Block Header ERR_RPT_BH Field Descriptions Bit Field Value Description 31 16 EF_PTR Hard wired pointer to the next block in the data structure NONE EXISTS 15 0 EF_ID Hard wired Extended Features ID Serial RapidIO SRIO 190 SPRU976 March 2006 Submit Documentation Feedback ...

Page 191: ...an invalid size or segment MSG logical endpoint MAT device only Write 0 to clear 27 ILL_TRANS_DEC Received illegal fields in the request response packet for a supported transaction IO MSG GSM ODE logical switch or endpoint device Write 0 to clear 26 ILL_TRANS_TRG Received a packet that contained a destination ID that is not defined for this endpoint NOT T_ERR SUPPORTED _ PACKET DESTROYED BEFORE RE...

Page 192: ...ng of an illegal transaction decode error Save and lock transaction capture _ENABLE information in Logical Transport Layer Device ID and Control Capture CSRs switch or end point device 26 ILL_TRANS_TARGET_ Enable reporting of an illegal transaction target error Save and lock transaction capture ERR_ENABLE information in Logical Transport Layer Device ID and Control Capture CSRs endpoint device onl...

Page 193: ...lue after reset 15 0 ADDRESS_63_32 R 0x00 LEGEND R Read only n value after reset Table 119 Logical Transport Layer High Address Capture CSR H_ADDR_CAPT Field Descriptions Bit Field Value Description 31 0 ADDRESS_63_3 Most Significant 32 bits of the address associated with the error only valid for devices supporting 2 66 and 50 bit addresses SPRU976 March 2006 Serial RapidIO SRIO 193 Submit Documen...

Page 194: ... Reserv XAMSBS ed R 0x00 R R 0x00 0x00 LEGEND R Read only n value after reset Table 120 Logical Transport Layer Address Capture CSR ADDR_CAPT Field Descriptions Bit Field Value Description 31 3 ADDRESS_31_3 Least Significant 29 bits of the address associated with the error 2 Reserved Reserved 1 0 XAMSBS Extended address bits of the address associated with the error Serial RapidIO SRIO 194 SPRU976 ...

Page 195: ...Table 121 Logical Transport Layer Device ID Capture CSR ID_CAPT Field Descriptions Bit Field Value Description 31 24 MSB_DESTID Most significant byte of the destinationID associated with the error large transport systems only 23 16 DESTID The destinationID associated with the error 15 8 MSB_SOURCEID Most significant byte of the source ID associated with the error large transport systems only 7 0 S...

Page 196: ...r reset Table 122 Logical Transport Layer Control Capture CSR CTRL_CAPT Field Descriptions Bit Field Value Description 31 28 FTYPE Format type associated with the error 27 24 TTYPE Transaction type associated with the error 23 16 MSGINFO Letter mbox and msgseg for the last Message request received for the mailbox that had an error Message errors only 15 0 IMP_SPECIFIC Implementation specific infor...

Page 197: ... Reserved R 0x00 LEGEND R Read only n value after reset Table 123 Port Write Target Device ID CSR PW_TGT_ID Field Descriptions Bit Field Value Description 31 24 DEVICEID_MSB This is the most significant byte of the port write target device ID large transport systems only 23 16 DEVICEID This is the port write target deviceID 15 0 Reserved Reserved SPRU976 March 2006 Serial RapidIO SRIO 197 Submit D...

Page 198: ...L Received a control symbol with a bad CRC value serial _SYM 21 CNTL_SYM_UNE Received an acknowledge control symbol with an unexpected ackID packet accepted or XPECTED_ACKI packet retry The Capture Registers don t have valid information during this error detection D 20 RCVD_PKT_NOT Received packet not accepted acknowledge control symbol _ACCPT 19 PKT_UNEXPECT Received packet with unexpected ackID ...

Page 199: ...served Reserved 23 Reserved Reserved 22 CORRUPT_CNTL_SYM_E Enable error rate counting of a corrupt control symbol NABLE 21 CNTL_SYM_UNEXPECTE Enable error rate counting of an acknowledge control symbol with an unexpected ackID D_ACKID_EN 20 RCVED_PKT_NOT_ACCPT Enable error rate counting of received packet not accepted control symbols _EN 19 PKT_UNEXPECTED_ACKI Enable error rate counting of packet ...

Page 200: ...nformation logged 00 Packet 01 Control symbol only error capture register 0 is valid 10 Implementation specific capture register contents are implementation specific 11 Undefined S bit error capture as if a packet parallel physical layer only 29 Reserved Reserved 28 24 ERROR_TYPE Encoded value of captured error bit in the Port n Error Detect Register 23 4 IMP_SPECIFIC Implementation Dependent Erro...

Page 201: ...1 SPn_ERR_CAPT_DBG1 31 16 CAPTURE0 R 0x00 LEGEND R Read only n value after reset 15 0 CAPTURE0 R 0x00 LEGEND R Read only n value after reset Table 127 Port n Packet Control Symbol Error Capture CSR 1 SPn_ERR_CAPT_DBG1 Field Descriptions Bit Field Value Description 31 0 CAPTURE0 Control Character and Control Symbol or 0 to 3 Bytes of Packet Header SPRU976 March 2006 Serial RapidIO SRIO 201 Submit D...

Page 202: ...l Error Capture CSR 2 SPn_ERR_CAPT_DBG2 31 16 CAPTURE1 R 0x00 LEGEND R Read only n value after reset 15 0 CAPTURE1 R 0x00 LEGEND R Read only n value after reset Table 128 Port n Packet Control Symbol Error Capture CSR 2 SPn_ERR_CAPT_DBG2 Field Descriptions Bit Field Value Description 31 0 CAPTURE1 4 to 7 Bytes of Packet Header Serial RapidIO SRIO 202 SPRU976 March 2006 Submit Documentation Feedbac...

Page 203: ... Error Capture CSR 3 SPn_ERR_CAPT_DBG3 31 16 CAPTURE2 R 0x00 LEGEND R Read only n value after reset 15 0 CAPTURE2 R 0x00 LEGEND R Read only n value after reset Table 129 Port n Packet Control Symbol Error Capture CSR 3 SPn_ERR_CAPT_DBG3 Field Descriptions Bit Field Value Description 31 0 CAPTURE2 8 to 11 Bytes of Packet Header SPRU976 March 2006 Serial RapidIO SRIO 203 Submit Documentation Feedbac...

Page 204: ... Error Capture CSR 4 SPn_ERR_CAPT_DBG4 31 16 CAPTURE3 R 0x00 LEGEND R Read only n value after reset 15 0 CAPTURE3 R 0x00 LEGEND R Read only n value after reset Table 130 Port n Packet Control Symbol Error Capture CSR 4 SPn_ERR_CAPT_DBG4 Field Descriptions Bit Field Value Description 31 0 CAPTURE3 12 to 15 Bytes of Packet Header Serial RapidIO SRIO 204 SPRU976 March 2006 Submit Documentation Feedba...

Page 205: ...t every 100ms 0x0F Decrement every 1s nominal 0x1F Decrement every 10s nominal 0x3F Decrement every 100s nominal 0x7F Decrement every 1000s nominal 0xFF Decrement every 10000s nominal Other values are reserved 23 18 Reserved Reserved 17 16 ERROR_RATE_R These bits limit the incrementing of the error rate counter above the failed threshold trigger ECOVERY 00b Only count 2 errors above 01b Only count...

Page 206: ...OR_RATE_F These bits provide the threshold value for reporting an error condition due to a possibly broken link AILED_THRESH OLD 0x00 Disable the error rate register 0x01 Set the error reporting threshold to 1 0x02 Set the error reporting threshold to 2 0xFF Set the error reporting threshold to 255 23 16 ERROR_RATE_D These bits provide the threshold value for reporting an error condition due to a ...

Page 207: ...or the link partner to enter its MER DISCOVERY state and if the link partner is supporting 4x mode for all 4 lanes to be aligned 0000b 102 4pS for debug only 0001b 0 84ms 0010b 0 84ms 2 1 68ms 1001b 0 84ms 9 7 56ms default 1111b 0 84ms 15 12 6ms 27 24 Reserved Reserved 23 20 PW_TIMER Port Write Timer The timer defines a period to repeat sending an error reporting Port Write request for software as...

Page 208: ...wable The 4 deep FIFO is used to accommodate the phase difference 27 PW_DIS Port Write Disable 0 Enable Port Write Error reporting default 1 Disable Port Write Error reporting 26 TGT_ID_DIS Destination ID Decode Disable Definition of packet acceptance by the physical layer 0 Packet accepted if DestID Base ID When DestID is not equal to Base ID the packet is ignored i e it is accepted by RapidIO po...

Page 209: ...equence Once set it remains set until written with logic 1 to clear The rst_irq output signal is driven by this bit 1 PW_EN Port Write In Interrupt Enable If enabled the interrupt signal is High when the Port Write In request is received 0b Port Write In interrupt disable 1b Port Write In interrupt enable 0 PW_IRQ Port Write In Request interrupt is set when the Port Write In request is received Th...

Page 210: ... only n value after reset Table 135 Serial Port IP Prescalar IP_PRESCAL Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 0 PRESCALE For different frequencies of the DMA clock use the formula DMA freq 16 156 25 _ 1 to get the prescalar value in decimal where DMA freq is in MHz 06h 66 67 MHz 09h 100MHz 10h 166 67MHz 18h 250MHz 21h 333Mhz Serial RapidIO SRIO 210 SPRU976 March 2...

Page 211: ...Capture CSR n SP_IP_PW_IN_CAPTn 31 16 PW_CAPTn R 0x00 LEGEND R Read only n value after reset 15 0 PW_CAPTn R 0x00 LEGEND R Read only n value after reset Table 136 Port Write In Capture CSR n SP_IP_PW_IN_CAPTn Field Descriptions Bit Field Value Description 31 0 PW_CAPT Port Write payload word n SPRU976 March 2006 Serial RapidIO SRIO 211 Submit Documentation Feedback ...

Page 212: ...00 R Undefined LEGEND R Read only n value after reset Table 137 Port Reset Option CSR n SPn_RST_OPT Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 0 PORT_ID Port ID defines unique number for port in Switch The Port ID is used for Port_Write request The ID coincides with ISF port of connection Example 00_0000_01 _ port 1 Impl IP0 port 1 00_0001_11 _ port 7 Impl IP1 port 3 S...

Page 213: ...he hardware recovery is disabled and the hardware transmission logic must wait until software has written the register Port n Local ackID Status CSR 28 27 Reserved Reserved 26 FORCE_REINIT Force reinitialization process In 4x mode this bit affects all 4 lanes This bit is write only read always 0 25 24 TRANS_MODE Describes the transfer mode for each port 00 Reserved Cut Through Mode 01 Store Forwar...

Page 214: ...to the register SP0_ERR_DET This error also reported in register SP0_ERR_DET 15 8 MAX_RETRY_TH Maximum Retry Threshold Trigger These bits provide the threshold value for reporting an error R condition due to possibly broken partner behavior 00 Disable the max_retry_error reporting 01 Set the max_retry_threshold to 1 02 Set the max_retry_threshold to 2 FF Set the max_retry_threshold to 255 7 IRQ_EN...

Page 215: ...e after reset 15 0 Reserved R 0x00 LEGEND R Read only n value after reset Table 139 Port Silence Timer n SPn_SILENCE_TIMER Field Descriptions Bit Field Value Description 31 28 SILENCE_TIMER Silence timer Defines the time of the port in the SILENT state 0000b 64ns for debug 0001b 13 1us 0010b 13 1us 2 26 2us 1011b 13 1us 11 144 1us default 1111b 13 1us 15 196 5us 27 0 Reserved Reserved SPRU976 Marc...

Page 216: ...er n SPn_MULT_EVNT_CS 31 16 MULT_EVNT_CS W 0x00 LEGEND R Read only n value after reset 15 0 MULT_EVNT_CS W 0x00 LEGEND R Read only n value after reset Table 140 Port Multicast Event Control Symbol Request Register n SPn_MULT_EVNT_CS Field Descriptions Bit Field Value Description 31 0 MULT_EVNT_CS Write to send Control Symbol data is ignored read 0x000000 Serial RapidIO SRIO 216 SPRU976 March 2006 ...

Page 217: ...l Symbol Transmit n SPn_CS_TX Field Descriptions Bit Field Value Description 31 29 STYPE_0 Encoding for control symbol that makes use of parameters PAR_0 and PAR_1 28 24 PAR_0 Used in conjunction with stype0 encoding 23 19 PAR_1 Used in conjunction with stype0 encoding 18 16 STYPE_1 Encoding for control symbol that makes use of parameter CMD 15 13 CMD Used in conjunction with stype1 encoding to de...

Page 218: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

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