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5.80
Port General Control CSR (SP_GEN_CTL)
SRIO Registers
Figure 136. Port General Control CSR (SP_GEN_CTL)
31
30
29
28-16
HOST
MAST
DISCO
Reserved
ER_E
VERE
NABL
D
E
RW-
RW-
RW-
R-0x00
0x00
0x00
0x00
LEGEND: R = Read only; -n = value after reset
15-0
Reserved
R-0x00
LEGEND: R = Read only; -n = value after reset
Table 110. Port General Control CSR (SP_GEN_CTL) Field Descriptions
Bit
Field
Value
Description
31
HOST
A Host device is a device that is responsible for system exploration, initialization, and maintenance.
Agent or slave devices are typically initialized by Host devices.
0b
Agent or Slave device
1b
Host device
30
MASTER_ENABL
The Master Enable bit controls whether or not a device is allowed to issue requests into the system.
E
If the Master Enable is not set, the device may only respond to requests.
0b
Processing element cannot issue requests
1b
Processing element can issue requests
29
DISCOVERED
This device has been located by the processing element responsible for system configuration.
0b
The device has not been previously discovered
1b
The device has been discovered by another processing element
28-0
Reserved
Reserved
Serial RapidIO (SRIO)
182
SPRU976 – March 2006
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