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SLVS695D – JUNE 2007 – REVISED JANUARY 2015
7.7 Switching Characteristics: V
DD
= 3 V
V
DD
= 3 V, T
J
= –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
(1)
MAX
UNIT
t
PLH1
Low-to-high propagation delay time, CLK to OUTn
40
65
95
ns
t
PLH2
Low-to-high propagation delay time, LE(ED1) to OUTn
40
65
95
ns
t
PLH3
Low-to-high propagation delay time, OE(ED2) to OUTn
40
65
95
ns
t
PLH4
Low-to-high propagation delay time, CLK to SDO
12
20
30
ns
t
PHL1
High-to-low propagation delay time, CLK to OUTn
300
365
ns
t
PHL2
High-to-low propagation delay time, LE(ED1) to OUTn
300
365
ns
t
PHL3
High-to-low propagation delay time, OE(ED2) to OUTn
300
365
ns
t
PHL4
High-to-low propagation delay time, CLK to SDO
12
20
30
ns
t
w(CLK)
Pulse duration, CLK
20
ns
t
w(L)
Pulse duration, LE(ED1)
20
ns
t
w(OE)
Pulse duration, OE(ED2)
500
ns
V
IH
= V
DD
, V
IL
= GND,
t
w(ED2)
Pulse duration, OE(ED2) in Error Detection Mode
2
μ
s
R
ext
= 360
Ω
, V
L
= 4 V,
R
L
= 44
Ω
, C
L
= 10 pF,
t
h(ED1,ED2)
Hold time, LE(ED1) and OE(ED2)
10
ns
CG = 0.992
t
h(D)
Hold time, SDI
2
ns
t
su(D,ED1)
Setup time, SDI, LE(ED1)
3
ns
t
su(ED2)
Setup time, OE(ED2)
8.5
ns
t
h(L)
Hold time, LE(ED1), Normal Mode
15
ns
t
su(L)
Setup time, LE(ED1), Normal Mode
15
ns
t
r
Rise time, CLK
(2)
500
ns
t
f
Fall time, CLK
(2)
500
ns
t
or
Rise time, outputs (off)
40
85
105
ns
t
or
Rise time, outputs (off), T
J
= 25°C
83
100
ns
t
of
Rise time, outputs (on)
100
280
370
ns
t
of
Rise time, outputs (on), T
J
= 25°C
170
225
ns
f
CLK
Clock frequency
Cascade operation
30
MHz
(1)
Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2)
If the devices are connected in cascade and t
r
or t
f
is large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
Copyright © 2007–2015, Texas Instruments Incorporated
7
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