1
2
3
4
5
1
0
1
1
1
0
0
0
0
0
Actual Mode
(Normal or Special)
Mode
Switching
Normal
Mode
CLK
OE(ED2)
LE(ED1)
Phase
1
2
3
4
5
1
0
1
1
1
1
0
0
0
0
Actual Mode
(Normal or Special)
Mode
Switching
Special
Mode
CLK
OE(ED2)
LE(ED1)
Phase
Switching to Special Mode
Switching to Normal Mode
SLVS695D – JUNE 2007 – REVISED JANUARY 2015
Figure 16. Mode Switching
As shown in
, once a one-clock-wide short pulse (101) of OE(ED2) appears, TLC591x enters the Mode
Switching phase. At the fourth rising edge of CLK, if LE(ED1) is sampled as voltage high, TLC591x switches to
Special Mode; otherwise, it switches to Normal Mode. The signal LE(ED1) between the third and the fifth rising
edges of CLK cannot latch any data. Its level is used only to determine into which mode to switch. However, the
short pulse of OE(ED2) can still enable the output ports. During mode switching, the serial data can still be
transferred through SDI and shifted out from SDO.
NOTE
1. The signal sequence for the mode switching may be used frequently to ensure that TLC591x is
in the proper mode.
2. The 1 and 0 on the LE(ED1) signal are sampled at the rising edge of CLK. The X means its
level does not affect the result of mode switching mechanism.
3. After power on, the default operation mode is Normal Mode.
9.4.1.1 Normal Mode Phase
Serial data is transferred into TLC591x through SDI, shifted in the Shift Register, and output via SDO. LE(ED1)
can latch the serial data in the Shift Register to the Output Latch. OE(ED2) enables the output drivers to sink
current. These functions differ only as described in Operation Mode Switching, in which case, a short pulse
triggers TLC591x to switch the operation mode. However, as long as LE(ED1) is high in the Mode Switching
phase, TLC591x remains in the Normal Mode, as if no mode switching occurred.
9.4.1.2 Special Mode Phase
In the Special Mode, as long as OE(ED2) is not low, the serial data is shifted to the Shift Register via SDI and
shifted out via SDO, as in the Normal Mode. However, there are two differences between the Special Mode and
the Normal Mode, as shown in the following sections.
9.4.2 Reading Error Status Code in Special Mode
When OE(ED2) is pulled low while in Special Mode, error detection and load error status codes are loaded into
the Shift Register, in addition to enabling output ports to sink current.
shows the timing sequence for
error detection. The 0 and 1 signal levels are sampled at the rising edge of each CLK. At least three zeros must
be sampled at the voltage low signal OE(ED2). Immediately after the second zero is sampled, the data input
source of the Shift Register changes to the 8-bit parallel Error Status Code register, instead of from the serial
data on SDI. Normally, the error status codes are generated at least 2
μ
s after the falling edge of OE(ED2). The
occurrence of the third or later zero saves the detected error status codes into the Shift Register. Therefore,
when OE(ED2) is low, the serial data cannot be shifted into TLC591x through SDI. When OE(ED2) is pulled high,
the data input source of the Shift Register is changed back to SDI. At the same time, the output ports are
disabled and the error detection is completed. Then, the error status codes saved in the Shift Register can be
shifted out via SDO bit by bit along with CLK, as well as the new serial data can be shifted into TLC591x through
SDI.
Copyright © 2007–2015, Texas Instruments Incorporated
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