Stellaris® LM3S9B96 Development Kit User’s Manual
September 5, 2010
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Memory Port Register
The MPORT register allows sequential video/graphics memory plane access. A write (read) to this
port generates a memory write (read) to the memory location calculated as follows:
Mem address = {MPH:MPL} + MPR x MPS + MPC.
After the transfer, if the MPC is not at the last pixel of the row, it automatically increments by 1. If
the MPC is at the last pixel of the row, it sets to 0 and the MPR is incremented by MPS.
Memory Window Register
Use the MEMPAGE register to select the active page (1 Kbyte page).
Loading a New Image to the FPGA
The FPGA can be re-imaged using any of the JTAG tool chains that support the Xilinx Spartan 3e
XC3S100e. Two standard JTAG interfaces are provided with the FPGA expansion board: 2 x 7
with 2mm pitch and 1 x 6 with .1" pitch. Once connected, your JTAG scan chain should show an
XC3S100e FPGA and an XCF01S PROM.
NOTE: Images loaded into the PROM must be set to use CCLK as the startup clock. Images
loaded direct to the FPGA may use either CCLK or JTAG CLK.
Figure F-4.
FPGA Boundary Scan
NOTE: The LM3S9B96 FPGA boots in JTAG mode, but transitions to serial mode once
configured by the PROM. If your programmer is JTAG-only, you may need to clear the
PROM and power cycle before you can directly program the FPGA via JTAG. This issue is
rare since most tools support both modes. Check with your tool manufacturer for updates.
Summary of Contents for Stellaris LM3S9B96
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