Stellaris® LM3S9B96 Development Kit User’s Manual
September 5, 2010
57
Interrupt Enable Register
The Interrupt Enable register masks or enables interrupts from the FPGA to the Stellaris
LM3S9B96 microcontroller. Masked interrupts will not assert the IRQ line, but they will still appear
in the Interrupt Status Register.
Bit Name
Description
VCFSIE
Video capture frame start interrupt enable.
VCFEIE
Video capture frame end interrupt enable.
VRMIE
Video capture row match interrupt enable.
LTSIE
LCD transfer start interrupt enable.
LTEIE
LCD transfer end interrupt enable.
LRMIE
LCD display row match interrupt enable.
Interrupt Status Register
The Interrupt Status register reports and clears interrupts from the camera and LCD systems.
An interrupt latches its corresponding bit high until cleared by writing a 1 to it.
Bit Name
Description
VCFSI
Video capture frame start interrupt. Clear the interrupt by setting the
corresponding bit to 1. Setting the bit to 0 has no effect.
Table F-4. Interrupt Enable Register
IRQEN: 0xA000.0004
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
0
LRMIE
LTEIE
LTSIE
VRMIE
VCFEIE
VCFSIE
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Table F-5. Interrupt Status Register
IRQSTAT: 0xA000.0006
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
0
LRMI
LTEI
LTSI
VRMI
VCFEI
VCFSI
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Summary of Contents for Stellaris LM3S9B96
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