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September 5, 2010
8-bit Latch
This 8-bit latch is used to store the lower 8-bits of the address, which are transmitted during the
address phase of an EPI transfer. The EPI must be configured in Host bus 8 mode 0 mode (HB8
ADMUX), with EPI30 configured as an Address Latch Enable (ALE) signal to control this latch.
Flash Memory
The Flash memory used is a 64 Mbit, 90-nsec Spansion S29GL064N90TFI040. This 8/16 bit
memory is used in 8-bit mode. Note that MA27 is used as a chip select signal for this memory.
SRAM
The SRAM used is an 8 Mbit, 45 nsec Cypress Semiconductor CY62158EV30LL-45ZSX, which is
an 8-bit memory. Note that MA27 and MA26 are used as chip selects for this memory.
I
2
C Memory
This I
2
C serial memory is used for storing configuration data. This is a 1 kilobit On-Semiconductor
memory.
LCD I/F, Power (Schematic 2 on page 48)
Page 2 of the schematics shows the LCD_DECODE CPLD, LCD interface connector, and the
3.3 V regulator.
LCD_DECODE CPLD
The LCD DECODE CPLD provides address latch and decode for the LCD interface. The LCD
Command and Data registers are mapped on the EPI memory space to streamline access to
these registers. The LCD panel control signals L_RDn, L_RWn, and L_DC and the L_D bus are
controlled by decode logic on the CPLD with timing derived from EPI signals and do not require
direct control from the microcontroller. The LCD latch register is provided to control the XN and YN
signals used for the touchscreen and also the reset signal to the LCD.
The LCD backlight signal L_BL is controlled by the Stellaris GPIO PE2 (
MA[24]
). PE2 can be
programmed as a GPIO for ON/OFF control of the LCD. A second option is to configure PE2 for
use as CCP2 or CCP4 with a PWM output for brightness control.
The TP1-TP4 testpoints connect to the CPLD JTAG signals and, along with TP5 and TP6, provide
an interface for test and programming of the CPLD.
LCD Interface Connector
The LCD Interface Connector J2 is a 2x17 socket that connects to headers JP16-JP31 and JP39
on the DK-LM3S9B96. All signals previously driven to the LCD from the Stellaris MCU are
replaced by equivalent signals driven from the LCD_DECODE CPLD.
DC Regulator
DC regulator U4 receives 5 V from the EPI connector and provides 3.3 V for the board. LED D1
provides a power indicator and lights when the regulator is providing power to the board.
Summary of Contents for Stellaris LM3S9B96
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