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September 5, 2010

 

Hardware Description

The block diagram for the EM2 expansion board is shown in Figure G-7.

Figure G-7. EM2 Expansion Board Block Diagram

Primary EM Header

The primary EM header should always be used when only one EM module is installed unless 
otherwise indicated in the README First document for the EM module you are installing. 

The primary EM header connects three buses to the EPI connector that are also shared with the 
secondary EM header. These buses are I

2

C, UART1, and SPI. 

NOTE: The primary and secondary EM headers have a unique SPI chip select signal, but share 

the data and clock signals.

The primary EM header contains four GPIO connections to the EPI connector. These GPIOs can 
be used as inputs or outputs depending upon the EM module installed. In addition, four unique 
GPIOs are provided to each EM header.

EPI 

Connector

UART1

MOD1 GPIO

MOD2 GPIO

MOD1 SHUTDOWN

MOD2 SHUTDOWN

SPI

MOD1 SPI_CS

MOD2 SPI_CS

MOD_I2C

AD_I2C

+3.3 V

CAT24C01

EEPROM

32 KHZ 

OSC

/4

/4

/4

SDIO 

Header

I

2

Audio

Header

Analog

Audio

Header

I

2

Audio

Header

Analog

Audio

Header

+3. 3 V

I2C
UART

SPI

SHUT
DOWN

GPIO

+3. 3 V

I2C
UART

SPI

SHUT
DOWN

GPIO

SECONDARY

EM

HEADER

(MOD2)

PRIMARY

EM

HEADER

(MOD1)

Summary of Contents for Stellaris LM3S9B96

Page 1: ...DK LM3S9B96 05 Copyright 2009 2010 Texas Instruments User s Manual Stellaris LM3S9B96 Development Kit...

Page 2: ...is and StellarisWare are registered trademarks of Texas Instruments ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited Other names and brands may be claimed as the proper...

Page 3: ...n Board 21 Flash and SRAM Memory Expansion Board 21 FPGA Expansion Board 21 EM2 Expansion Board 21 Chapter 4 Using the In Circuit Debugger Interface 23 Appendix A Stellaris LM3S9B96 Development Board...

Page 4: ...FPGA 61 Installing the Software 62 Modifying the Default Image 62 Default FPGA Image Blocks 62 EPI Signal Descriptions 63 Component Locations 64 Schematics 65 Appendix G Stellaris LM3S9B96 EM2 Expans...

Page 5: ...re F 1 FPGA Expansion Board 49 Figure F 2 Removing EPI Board from DK LM3S9B96 Development Board 51 Figure F 3 FPGA Expansion Board Block Diagram 52 Figure F 4 FPGA Boundary Scan 61 Figure F 5 Componen...

Page 6: ...Switch Related Signals 19 Table C 1 Debug Interface Pin Assignments 35 Table D 1 Microcontroller GPIO Assignments 37 Table E 1 Flash and SRAM Memory Expansion Board Memory Map 45 Table E 2 LCD Latch...

Page 7: ...The Stellaris LM3S9B96 Development Kit accelerates development of Tempest class microcontrollers The kit also includes extensive example applications and complete source code Features The Stellaris LM...

Page 8: ...rd DK LM3S9B96 FS8 sold separately Provides Flash memory SRAM and an improved performance LCD interface For more information on the DK LM3S9B96 FS8 memory expansion board see Appendix E Stellaris LM3S...

Page 9: ...6 Microcontroller CAN Bus Interface 3 5 LCD Touch Panel USB connector with Host Device and On the Go modes 10 100 Ethernet User LED microSD Card Slot Potentiometer 5 VDC supply input JTAG SWD In Out C...

Page 10: ...OTG to PC connection USB Micro A to USB A adapter for USB Host USB Flash memory stick microSD Card 20 position ribbon cable CD containing A supported version of one of the following including a toolc...

Page 11: ...power output 3 3 Vdc 100 mA max USB USB USB T Stellaris Tempest class LM3S9B96 Microcontroller QVGA Color LCD Module I O Signal Break out Switch LED Tempest LM 3S9B96 Development Board I O Signal Brea...

Page 12: ...board Analog Reference 3 0 V 0 2 RoHS status Compliant NOTE When the LM3S9B96 Development Board is used in USB Host mode the host connector is capable of supplying power to the connected USB device Th...

Page 13: ...e jumpers The jumpers must be in these positions for the quickstart demo program to function correctly The development board offers capabilities that the LM3S9B96 cannot support simultaneously due to...

Page 14: ...mper that serves no function other than to provide a convenient place to park a spare jumper This jumper may be reused as required Figure 2 1 Factory Default Jumper Settings Clocking The development b...

Page 15: ...power rails A 3 3 V supply powers the microcontroller and most other circuitry 5 V is used by the OTG USB port and In circuit Debug Interface ICDI USB controller A low drop out LDO regulator U5 conve...

Page 16: ...ink or Keil ULINK Most debuggers use Pin 1 of the Debug connector to sense the target voltage and in some cases power the output logic circuit Installing the VDD PIN1 jumper will apply 3 3 V power to...

Page 17: ...can route the SWO datastream to the VCP transmit channel The debugger software can then decode and interpret the trace information received from the Virtual Com Port The normal VCP connection to UART0...

Page 18: ...nstant current mode its output voltage will jump up if the LCD should become disconnected To prevent over voltage failure of the IC or diode D3 a zener D4 clamps the voltage The current will limit to...

Page 19: ...y standard headphones The Line Output is suitable for connection to an external amplifier including PC desktop speaker sets User Switch and LED The development board provides a user push switch and LE...

Page 20: ...20 September 5 2010...

Page 21: ...Flash and SRAM Memory Expansion Board sold separately see Appendix E Stellaris LM3S9B96 Flash and SRAM Memory Expansion Board on page 41 FPGA Expansion Board The FPGA Expansion Board DK LM3S9B96 FPGA...

Page 22: ...22 September 5 2010...

Page 23: ...and an external Stellaris microcontroller The only requirement is that the correct Stellaris device is selected in the project configuration The Stellaris target board should have a 2x10 0 1 pin head...

Page 24: ...24 September 5 2010...

Page 25: ...cs for the DK LM3S9B96 development board Micro EPI connector USB and Ethernet on page 26 LCD CAN Serial Memory and User I O on page 27 Power Supplies on page 28 I2 S Audio Expansion Board on page 29 E...

Page 26: ...PD6 PD7 PB6 TXSCK AVREF PB7 NMI PF0 PF1 TXMCLK LED2 JP2 PF3 LED0 VBUS D D ID G 1 2 3 4 G2 5 G1 J3 USB Micro AB USB On the Go VBUS PB0 USBID OTG ID JP4 VBUS JP3 PB1 USBVBUS PA0 U0RX 26 PA1 U0TX 27 PA2...

Page 27: ...2 0 1UF C29 0 1UF QVGA LCD Panel with touch interface LCD_D 0 7 C28 0 01UF C30 0 01UF C31 0 01UF C33 0 01UF 3 3V R12 50K ILED C23 0 1UF R14 10K 3 3V 8 bit 8080 mode PE6 ADC1 PE3 EPI25 PE2 EPI24 PE7 AD...

Page 28: ...UF R26 15 R25 10K ILED 24V D4 BZT52C24 5V EPEN JP37 PFLT JP38 Backlight JP39 PA7 USBPFLT CAN0TX PA6 USBEPE CAN0RX USB0EPE USB0PFLT 0 01UF C39 C42 2 2UF C37 2 2UF VOUT 5 NR 1 ON 3 GND 2 VIN 4 U5 PQ1LA3...

Page 29: ...47K R34 47K C56 0 1UF C59 2 2UF C60 2 2UF C61 2 2UF C50 0 1UF 1 3 2 J9 STX 3000 R31 4 7K R28 10K 27PF C47 C48 2 2UF MICIN R30 10K MICBIAS Audio Headphone Output Microphone Input MCLK LRC RXSD BITCLK T...

Page 30: ...UF C64 0 01UF C63 0 01UF C66 0 1UF 3 3V Expansion Connector SDRAM Expansion Board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4...

Page 31: ...V D D ID G 1 2 3 4 7 5 6 J13 54819 0572 FT_SRSTN Debugger USB Interface R43 USBSH CS 1 SK 2 DI 3 DO 4 GND 5 ORG 6 NC 7 VCC 8 1K 64X16 U11 CAT93C46 1 2 Y3 6 00MHz 27PF C68 27PF C69 SWO_EN 0 01UF C67 2...

Page 32: ...32 September 5 2010...

Page 33: ...eptember 5 2010 33 Stellaris LM3S9B96 Development Board Component Locations This appendix contains details on component locations including Component placement plot for top Figure B 1 A P P E N D I X...

Page 34: ...34 September 5 2010 Figure B 1 Component Placement Plot for Top...

Page 35: ...ut and output mode the Stellaris LM3S9B96 Development Kit supports ARM s standard 20 pin JTAG SWD configuration The same pin configuration can be used for debugging over serial wire debug SWD and JTAG...

Page 36: ...36 September 5 2010...

Page 37: ...SI0Fss SD Card CSn 30 PA4 SSI0Rx SPI 31 PA5 SSI0Tx SPI 34 PA6 USB0EPEN USB Pwr Enable CAN0RX 35 PA7 USB0PFLT USB Pwr Fault CAN0TX 66 PB0 USB0ID USB OTG ID 67 PB1 USB0VBUS USB Vbus 72 PB2 I2C0SCL Audio...

Page 38: ...S25 6 PE4 I2STXWS I2S Audio Out 5 PE5 I2STXSD I2S Audio Out 2 PE6 ADC1 ADC Touch XP 1 PE7 ADC0 ADC Touch YP 47 PF0 PF0 Flash CSn 61 PF1 I2STXMCLK I2S Audio Out 60 PF2 LED1 Green Enet LED 59 PF3 PF3 Us...

Page 39: ...eakout 14 PJ0 EPI0S16 SDRAM DQM 87 PJ1 EPI0S17 SDRAM DQM 39 PJ2 EPI0S18 SDRAM CAS 50 PJ3 EPI0S19 SDRAM RAS 52 PJ4 EPI0S28 SDRAM WEn 53 PJ5 EPI0S29 SDRAM CSn 54 PJ6 EPI0S30 SDRAM SDCKE 55 PJ7 PJ7 User...

Page 40: ...40 September 5 2010...

Page 41: ...erface Figure E 1 Flash and SRAM Memory Expansion Board Features The DK LM3S9B96 EXP FS8 memory expansion board has the following features 8 Megabytes of Flash memory 1 Megabyte of SRAM Memory mapped...

Page 42: ...on standoffs on mounting holes above the EPI connector J2 5 Place the expansion board on top of the DK LM3S9B96 board and align the standoffs the EPI connector and the 2x17 J2 header 6 Press firmly do...

Page 43: ...section The first page of the schematics shows the memory devices and address latch part of the design The second page shows the LCD I F and regulator Flash SRAM Schematic 1 on page 47 Page 1 of the s...

Page 44: ...are mapped on the EPI memory space to streamline access to these registers The LCD panel control signals L_RDn L_RWn and L_DC and the L_D bus are controlled by decode logic on the CPLD with timing de...

Page 45: ...Y input to the touchscreen RST When clear the L_RSTN signal is set to clear When set the L_RSTN signal is reset This signal is used to reset the LCD panel Table E 1 Flash and SRAM Memory Expansion Bo...

Page 46: ...hows the details of the component locations Figure E 4 Component Placement Plot for Top and Bottom Schematics This section shows the schematics for the DK LM3S9B96 EXP FS8 memory expansion board Flash...

Page 47: ...C4 0 1uF C5 0 1uF C1 0 1uF 3 3V C10 0 1uF R5 2 80k 3 3V R6 2 80k I2CSCL I2CSDA MA19 MA20 MA21 MA22 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 A0 5 DQ0 9 A1 4 A2 3 A3 2 A4 1 A5 44 A6 43 A7 42 A8 39 A9 28...

Page 48: ...B5 26 B6 27 B7 28 B8 31 B9 32 B10 33 B11 34 B12 38 B13 39 B14 40 A12 14 A13 15 A14 16 A15 17 TDI 1 TCK 11 TMS 25 TDO 35 GND01 5 GND1 13 GND11 29 GND2 37 VCC01 6 VCC1 12 VCC11 30 VCC2 36 A11 10 CLK2 I...

Page 49: ...of the FPGA expansion board Figure F 1 FPGA Expansion Board Features The LM3S9B96 FPGA memory expansion board has the following features Xilinx Spartan 3E FPGA with 100k system gates 1 13 CMOS VGA 640...

Page 50: ...board remove the shunt jumpers on JP16 JP31 and the JP39 headers as shown in Figure F 1 on page 49 4 Place the expansion board on top of the DK LM3S9B96 board and press firmly downward until the board...

Page 51: ...tellaris LM3S9B96 Development Kit User s Manual September 5 2010 51 Figure F 2 Removing EPI Board from DK LM3S9B96 Development Board Remove board Remove JP16 31 5 V Power Remove POT PB4 jumpers jumper...

Page 52: ...era provides color VGA images at up to 30 frames per second to the FPGA over an 8 bit wide parallel interface It is configured by the Stellaris microcontroller via I2 C SRAM The 1 MB 8 bit wide 10 ns...

Page 53: ...LCD header pins should fit through the holes on the PCB 24 MHz Oscillator The camera and the camera interface portion of the FPGA are clocked by a 24 MHz external oscillator External Peripheral Interf...

Page 54: ...OTE Ten bits are used for addressing but the EPI controller allocates a 12 bit address space The result is that 0x0A00 0000 is equivalent to 0x0A00 0400 0x0A00 0800 and 0x0A00 0C00 Table F 1 FPGA Expa...

Page 55: ...is only valid after being initialized as described above RTL Version Revision level of the code running in the FPGA expansion board LGML 050 15 0 LCD Graphics Memory Address Low R W 60 LGMH 052 4 0 LC...

Page 56: ...ny read or write to the memory port auto increments the MPC register at the end of the transfer by 1 If MPC is at the last column MPNR 1 then it sets to 0 and the MPR increments by 1 If the end of the...

Page 57: ...isplay row match interrupt enable Interrupt Status Register The Interrupt Status register reports and clears interrupts from the camera and LCD systems An interrupt latches its corresponding bit high...

Page 58: ...he on board test pads TP1 TP8 which are connected to unused FPGA pins Bit Name Description TP1 TP3 Test Pins 1 3 These are connected to FPGA I O pins Writing a 1 sets the corresponding test pin output...

Page 59: ...he output instead Video Capture Row Match Register During video capture at the start of a row the current row value is compared with the VCRM register A match generates an interrupt if enabled Video M...

Page 60: ...o the LCD and contains the higher 16 bits of the address LCD Graphics Memory Stride Register The LGMS register specifies the number of bytes between the first pixels on adjacent rows in LCD graphics m...

Page 61: ...he FPGA can be re imaged using any of the JTAG tool chains that support the Xilinx Spartan 3e XC3S100e Two standard JTAG interfaces are provided with the FPGA expansion board 2 x 7 with 2mm pitch and...

Page 62: ...camera capture block is given highest priority This is contained within the arb v file Video Compositor The video compositor assembles the final image from the video and graphics frame buffers and pa...

Page 63: ...rollera a Configure as Stellaris GPIO input with negative level sensitive interrupts During power up reset is used for PLL lock status EPIOS 29 PJ5 E_RD In EPI Read Strobe EPIOS 28 PJ4 E_WR In EPI Wri...

Page 64: ...Component Locations Figure F 5 shows the details of the component locations from the top view and Figure F 6 shows the details of the component locations from the bottom view Figure F 5 Component Pla...

Page 65: ...Kit User s Manual September 5 2010 65 Figure F 6 Component Placement Plot for Bottom Schematics This section shows the schematics for the LM3S9B96 FPGA memory expansion board EPI LCD Camera I F on pag...

Page 66: ...06N_2 M2 GCLK1 57 IP 69 IP 6 IP VREF_3 12 IP 18 IP 24 IP 36 IP VREF_2 66 IP VREF_3 31 U1E XC3S100E 4TQG144C EPI10 EPI28 EPI29 EPI30 EPI31 EPI13 EPI14 EPI16 EPI17 EPI19 EPI20 EPI21 EPI22 EPI23 EPI24 EP...

Page 67: ...C 44 WE 15 OE 37 CE 8 VSS 12 VSS 34 VDD 11 VDD 33 A19 25 NC_A20 42 1Mx8 U4 IS61WV10248 MA20 ALE1 ALE2 MCS_n MWE_n MOE_n BANK 3 IO 10 IO 29 IO_L10N_3 35 IO_L10P_3 34 IO_L09N_3 33 IO_L09P_3 32 IO_L08N_3...

Page 68: ...68 September 5 2010...

Page 69: ...s DK LM3S9B96 platform Figure G 1 EM2 Expansion Board Features The DK LM3S9B96 EM2 expansion board has the following features 2 sets of EM connectors to support up to 2 RF evaluation modules 1 kilobit...

Page 70: ...in uninstalled Figure G 2 Removing EPI Board from DK LM3S9B96 Development Board 3 Place the EM2 expansion board on top of the DK LM3S9B96 board while aligning the male EPI expansion connector on the b...

Page 71: ...ember 5 2010 71 Figure G 3 EM2 Expansion Board 4 Press firmly downward until the board snaps in place Figure G 4 Assembled DK LM3S9B96 Development Board with EM2 Expansion Board Male EPI expansion con...

Page 72: ...lot it should be installed in install the single module into the primary EM header MOD1 To install an EM module into the primary module EM slot of the EM2 expansion board do the following 1 Attach any...

Page 73: ...Assembled DK LM3S9B96 Board with EM2 Expansion Board and Wireless EM Module Follow these same steps for installing a second module into the secondary EM header location which will be oriented 180 degr...

Page 74: ...PI NOTE The primary and secondary EM headers have a unique SPI chip select signal but share the data and clock signals The primary EM header contains four GPIO connections to the EPI connector These G...

Page 75: ...PS1 I2S Header The primary EM header and the secondary EM header each contain connections to separate 6 pin I2 S headers J2 and J4 respectively These headers connect to the EM modules only and are not...

Page 76: ...C Bus to Auto Discovery EEPROM PC4 PC4 MOD1_nSHUTD Out Shutdown Reset Signal for Primary EM Module PH5 PH5 MOD2_nSHUTD Out Shutdown Reset Signal for Secondary EM Module PH0 PH0 MOD1_GPIO0 I O GPIO fo...

Page 77: ...r 5 2010 77 Component Locations Figure G 8 shows the details of the component locations Figure G 8 Component Placement Plot for Top and Bottom Schematics This section shows the schematics for the EM2...

Page 78: ...of DK LM3S9B96_EM2 DK LM3S9B96_EM2 DK LM3S9B96_EM2 DK LM3S9B96_EM2 C LM3S9B96 EM2 Adapter LM3S9B96 EM2 Adapter LM3S9B96 EM2 Adapter LM3S9B96 EM2 Adapter B 1 1 Monday July 12 2010 R15 2 7K R15 2 7K C4...

Page 79: ...number SW DRL UG Additional references include FT2232D Dual USB UART FIFO IC Data sheet version 0 91 2006 Future Technology Devices International Ltd Texas Instruments TLV320AIC23BPM Audio CODEC Data...

Page 80: ...80 September 5 2010...

Page 81: ...orized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parti...

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